公开(公告)号：US20240334690A1

公开(公告)日：2024-10-03

申请号：US18676298

申请日：2024-05-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou

IPC: H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Memory devices and methods for forming the same are disclosed. In certain aspects, a memory device includes a filling layer; a stack structure including interleaved conductive layers and dielectric layers; a channel structure extending through the stack structure and the filling layer. The channel structure includes a memory film and a semiconductor channel. The memory device also includes a doped semiconductor layer in contact with the semiconductor channel. The filling layer is between the doped semiconductor layer and the stack structure. The memory device further includes an insulating layer, and a source contact extending through the insulating layer and in contact with the doped semiconductor layer. The doped semiconductor layer is between the insulating layer and the filling layer.

公开(公告)号：US12048151B2

公开(公告)日：2024-07-23

申请号：US17020398

申请日：2020-09-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Ziqun Hua ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B41/40 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, a conductive layer in contact with upper ends of the plurality of channel structures, at least part of which is on the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer.

公开(公告)号：US12027207B2

公开(公告)日：2024-07-02

申请号：US17646549

申请日：2021-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： DongXue Zhao ,  Tao Yang ,  Yuancheng Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  ZongLiang Huo

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.

公开(公告)号：US20240215235A1

公开(公告)日：2024-06-27

申请号：US18092777

申请日：2023-01-03

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Zongliang Huo

IPC: H10B41/40 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a pad-out structure disposed on the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal in contact with the first side of the first semiconductor layer and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; and a plate line extending in the second direction.

公开(公告)号：US20240212753A1

公开(公告)日：2024-06-27

申请号：US18095336

申请日：2023-01-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Zongliang Huo

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.

公开(公告)号：US11910599B2

公开(公告)日：2024-02-20

申请号：US17993600

申请日：2022-11-23

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang Sun ,  Guangji Li ,  Kun Zhang ,  Ming Hu ,  Jiwei Cheng ,  Shijin Luo ,  Kun Bao ,  Zhiliang Xia

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

公开(公告)号：US11877453B2

公开(公告)日：2024-01-16

申请号：US17214390

申请日：2021-03-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Kun Zhang

IPC: H01L27/11582 ,  H01L27/11519 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B41/35 ,  H10B43/35

Abstract: A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, a plurality of channel holes penetrating the alternating layer stack, a channel structure in each channel hole, and a top selective gate cut structure having a laminated structure and located between two rows of channel structures.

公开(公告)号：US20230413570A1

公开(公告)日：2023-12-21

申请号：US17845443

申请日：2022-06-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Di Wang ,  Wei Liu ,  Zongliang Huo

IPC: H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional (3D) memory device includes a plurality of memory planes and a separation block. Each memory plane includes a plurality of memory blocks. Each memory block includes a memory stack including interleaved conductive layers and first dielectric layers, and a plurality of channel structures each extending through the memory stack. The separation block extending laterally to separate each two adjacent memory planes. Each separation block includes a dielectric stack including interleaved second dielectric layers and the first dielectric layers. The first dielectric layers extend across the memory blocks and the separation block, and the second dielectric layers separate the conductive layers of two adjacent memory blocks.

公开(公告)号：US20230413541A1

公开(公告)日：2023-12-21

申请号：US17843636

申请日：2022-06-17

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Shuangshuang Wu

IPC: H01L27/11556 ,  H01L27/11521

CPC classification number: H01L27/11556 ,  H01L27/11521

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. The 3D memory device includes a doped semiconductor layer, a source select gate line disposed on the doped semiconductor layer, a stack structure including interleaved conductive layers and dielectric layers formed on the source select gate line, and a channel structure extending through the stack structure and the source select gate line and in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel and a memory film. The source select gate line is in contact with the semiconductor channel.

公开(公告)号：US11837541B2

公开(公告)日：2023-12-05

申请号：US17093170

申请日：2020-11-09

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong Zhang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes an intermediate region and array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region. In the intermediate region, wall-structure regions of the first block and the second block are separated by a staircase structure. The memory device further includes a beam structure, located in the intermediate region and including at least a plurality of discrete first beam structures, each extending along the second lateral direction and connecting the wall-structure regions of the first block and the second block; and a plurality of second dielectric layers, located in the beam structure. In the first beam structures, the second dielectric layers is alternated with the first dielectric layers.