公开(公告)号：US06839219B2

公开(公告)日：2005-01-04

申请号：US10466886

申请日：2002-09-25

Applicant: Yasuaki Mashiko ,  Hideshi Sekimori ,  Naotomi Takahashi

Inventor： Yasuaki Mashiko ,  Hideshi Sekimori ,  Naotomi Takahashi

IPC: H01G4/10 ,  C25D11/04 ,  C25D11/18 ,  H01G4/12 ,  H01G4/33 ,  H05K1/16 ,  H05K3/46 ,  H01G4/06

CPC classification number: H01G4/1209 ,  C25D11/04 ,  C25D11/18 ,  H01G4/129 ,  H05K1/162 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0315 ,  Y10T428/24917

Abstract: An object of the present invention is to provide a laminate for forming a capacitor layer for a printed wiring board which is capable of ensuring a higher capacitance and an inner layer core material using the laminate for example. In order to achieve this object, a material for forming a capacitor layer comprising a three-layered structure of an aluminum layer 2/a modified alumina barrier layer 3/an electrode copper layer 4 is used, such as a laminate 1a for forming a capacitor layer in which the above described modified alumina barrier layer 3 is obtained through subjecting one side of an aluminum plate or aluminum foil to an anodic treatment to form an alumina barrier layer as a uniform oxide layer and then subjecting the alumina material with the above described alumina barrier layer formed thereon to a boiling and modifying treatment in water and the above described modified aluminum barrier layer 3 is used as a dielectric layer.

公开(公告)号：US20040227227A1

公开(公告)日：2004-11-18

申请号：US10820114

申请日：2004-04-08

Applicant: FUJITSU LIMITED ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Yoshihiko Imanaka ,  Jun Akedo ,  Maxim Lebedev

IPC: H01L023/053 ,  H01L021/8222

CPC classification number: H01L27/08 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/162 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/0209 ,  H05K2201/09672 ,  H05K2203/1366 ,  H01L2224/0401

Abstract: A circuit substrate includes a passive element and an interconnection pattern, wherein any of the passive element and the interconnection pattern is formed by an aerosol deposition process that uses aerosol of a fine particle material.

Abstract translation: 电路基板包括无源元件和互连图案，其中无源元件和互连图案中的任一个通过使用细颗粒材料气溶胶的气溶胶沉积工艺形成。

公开(公告)号：US20040173873A1

公开(公告)日：2004-09-09

申请号：US10801324

申请日：2004-03-16

Inventor： Prabhat Kumar ,  Henning Uhlenhut

IPC: H01L027/108 ,  H01L029/76

CPC classification number: H01G9/15 ,  H01G4/10 ,  H01G11/48 ,  H05K1/162 ,  H05K2201/0179 ,  H05K2201/0329 ,  H05K2201/09763 ,  Y02E60/13

Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film comprising an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film comprising an electrically conductive polymer located on the pentoxide layer.

Abstract translation: 本发明涉及一种薄膜电容器，其包含（a）基底，（b）第一聚合物膜，其包含位于基底上的导电聚合物，（c）五氧化物层，其选自五氧化二钽或五氧化二铌 ，及其混合物，（d）包含位于五氧化物层上的导电聚合物的第二聚合物膜。

公开(公告)号：US06673388B2

公开(公告)日：2004-01-06

申请号：US09844019

申请日：2001-04-27

Applicant: Thomas N. Blanton ,  Syamal K. Ghosh ,  Donn B. Carlton ,  Dilip K. Chatterjee

Inventor： Thomas N. Blanton ,  Syamal K. Ghosh ,  Donn B. Carlton ,  Dilip K. Chatterjee

IPC: B05D512

CPC classification number: H05K1/162 ,  C23C18/14 ,  H05K3/1241 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2203/0126 ,  H05K2203/0315 ,  H05K2203/107 ,  H05K2203/121

Abstract: A method of making a charge containing element including the steps of depositing and patterning a dielectric material on a surface wherein the dielectric material includes a metallo-organic component and a liquid component; and decomposing by laser light the deposited dielectric material to substantially evaporate the liquid component to cause the metallic portion of the metallo-organic component to react with oxygen causing the dielectric material to have charge-holding properties.

Abstract translation: 一种制造含电荷元素的方法，包括以下步骤：在介电材料包括金属有机组分和液体组分的表面上沉积和图案化电介质材料; 并通过激光分解沉积的电介质材料，以使液体组分基本蒸发，使金属 - 有机组分的金属部分与氧反应，导致电介质材料具有电荷保持性能。

公开(公告)号：US06671950B2

公开(公告)日：2004-01-06

申请号：US09901373

申请日：2001-07-09

Applicant: Lance C. Sturni ,  Kevin C. Olson

Inventor： Lance C. Sturni ,  Kevin C. Olson

IPC: H01K310

CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A process for fabricating a multi-layer circuit assembly is provided comprising the following steps: (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core; (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core; (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and (e) applying a resinous photosensitive layer to the metal layer. Additional processing steps such as circuitization may be included. Also provided are multi-layer circuit assemblies produced by the process of the present invention, comprising component layers having high via density and thermal coefficients of expansion that are compatible with those of semiconductor chips and rigid wiring boards which may be attached as components of the circuit assembly.

Abstract translation: 提供一种制造多层电路组件的方法，包括以下步骤：（a）提供具有500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的通孔密度的穿孔导电芯;（b ）在所述导电芯的所有暴露表面上施加电介质涂层以在所述导电芯的所有暴露表面上形成共形涂层;（c）以预定图案烧蚀所述电介质涂层的表面以暴露所述导电芯部分 芯;（d）将金属层施加到所有表面以通过导电芯形成金属化通孔; 另外还可以包括诸如电路化的其它处理步骤。还提供了通过本发明的方法生产的多层电路组件，其包括具有高通孔密度和热量的组分层 与可以作为电路组件的组件附接的半导体芯片和刚性线路板的扩展系数相容。

公开(公告)号：US06632591B2

公开(公告)日：2003-10-14

申请号：US09781462

申请日：2001-02-12

Applicant: Andrew T. Hunt ,  Wen-Yi Lin ,  Richard W. Carpenter

Inventor： Andrew T. Hunt ,  Wen-Yi Lin ,  Richard W. Carpenter

IPC: G03F700

CPC classification number: H05K1/162 ,  H05K1/167 ,  H05K3/4623 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0338 ,  H05K2203/1338 ,  Y10T428/24917

Abstract: Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material and layers of dielectric material. Outer resistive material layers are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material on opposite sides of the laminate act as capacitors. Electrical pathways horizontally through resistive material layers, which may be connected by via plated holes, act as resistors.

Abstract translation: 通过交替沉积，例如通过燃烧化学气相沉积（CCVD），电阻材料层和电介质材料层形成纳米级氨酸盐。 外部电阻材料层被图案化以形成电阻材料的离散贴片。 在层压板相对两侧的相对电阻材料片之间的电气通路用作电容器。 可通过电镀孔连接的电阻材料层的水平电路作为电阻

公开(公告)号：US20030066680A1

公开(公告)日：2003-04-10

申请号：US10256542

申请日：2002-09-26

Applicant: Alps Electric Co., Ltd.

Inventor： Katsuya Kikuiri ,  Takashi Takabatake

IPC: H05K001/09

CPC classification number: G11B5/3967 ,  G11B5/3103 ,  G11B5/3109 ,  G11B5/48 ,  G11B5/53 ,  H05K1/112 ,  H05K3/243 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09436 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0733

Abstract: A terminal electrode provided on a lead joint of a thin-film device fabricated by a thin-film technology. The terminal electrode is constituted by an upper pad and a lower pad, the lower pad being formed into a pillar-like shape protuberantly projecting from the lead joint. The upper pad, which is wider than the lower pad, is formed on the lower pad such that the center thereof is aligned with the center of the lower pad. This arrangement provides the terminal electrode that allows a higher-density insulating layer free of defects, such as voids, to be formed around the terminal electrode, leading to an improved mounting strength of the terminal electrode.

Abstract translation: 设置在通过薄膜技术制造的薄膜器件的引线接头上的端子电极。 端子电极由上焊盘和下焊盘构成，下焊盘形成为从引线接头突出地突出的柱状形状。 比下垫宽的上衬垫形成在下垫上，使得其中心与下垫的中心对准。 这种布置提供了允许在端子电极周围形成无空隙缺陷的更高密度绝缘层的端子电极，导致端电极的安装强度提高。

公开(公告)号：US06524352B2

公开(公告)日：2003-02-25

申请号：US10043830

申请日：2002-01-09

Applicant: Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

Inventor： Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

IPC: H01G900

CPC classification number: H05K1/053 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/162 ,  H05K3/403 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0919 ,  H05K2201/10378 ,  H05K2203/0315 ,  Y10T29/417 ,  H01L2924/00

Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

公开(公告)号：US6411194B2

公开(公告)日：2002-06-25

申请号：US79459601

申请日：2001-02-27

Applicant: VICTOR COMPANY OF JAPAN

Inventor： SHINDOH MOTOSHI ,  SEGAWA KEIJI ,  OTSUKI MITSURU

IPC: H01C17/12 ,  H05K1/02 ,  H05K1/16 ,  H05K3/38 ,  H05K3/46 ,  H01C1/012

CPC classification number: H05K1/167 ,  H01C17/12 ,  H05K1/0206 ,  H05K1/165 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: The invention provides a production method capable of forming a thin film resistance element having a thickness and a shape controlled in a high accuracy in a printed circuit board. The production method of a thin film resistance element formed on a printed circuit board, has the steps of forming a thin film resistance layer having a predetermined thickness on the printed circuit board through an insulation layer by a dry process used in producing a semiconductor, forming an electrically conductive layer on the thin resistance layer, and etching the electrically conductive layer selectively so as to make, at least, a pair of electrically conductive pads, resulting in the thin film resistance element having a predetermined value of resistivity between the pair of electrically conductive pads. Thereby, it is possible to form the thin film resistance element having a thickness and a shape controlled in a high accuracy on the printed circuit board.

Abstract translation: 本发明提供一种能够形成在印刷电路板中具有高精度的厚度和形状的薄膜电阻元件的制造方法。 形成在印刷电路板上的薄膜电阻元件的制造方法具有以下步骤：通过用于制造半导体的干法在印刷电路板上形成具有预定厚度的薄膜电阻层，形成 在所述薄电阻层上的导电层，并且选择性地蚀刻所述导电层，以便至少形成一对导电焊盘，导致所述薄膜电阻元件在所述一对电学上具有预定的电阻率值 导电垫。 因此，可以在印刷电路板上形成具有高精度的厚度和形状的薄膜电阻元件。

公开(公告)号：US20020066523A1

公开(公告)日：2002-06-06

申请号：US09730372

申请日：2000-12-05

Inventor： Lance L. Sundstrom ,  Kenneth H. Heffner

IPC: B29C031/00

CPC classification number: H01L24/83 ,  G02B6/4232 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/16237 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/28 ,  H05K3/321 ,  H05K2201/0179 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2201/10984 ,  H05K2203/1173 ,  H05K2203/306 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A surface treatment or mask that inhibits polymer whetting and bonding is applied to all but the mating bond areas of the interface between a substrate and a device. A polymer material is applied to the bond areas of either the substrate or the device. The device is placed onto the substrate such that the polymer material bridges the mating bond areas of both the substrate and the device. As the polymer material is cured, surface tension pulls it into a vertical column defined by the polymer mask defined mating bond areas of the substrate and device and aligns the mating bond areas directly over each other. Once cured, the polymer forms a mechanical bond and, depending upon the polymer material, forms an electrical, thermal and/or optical connection between the substrate and the device.

Abstract translation: 抑制聚合物磨损和粘合的表面处理或掩模施加到基底和器件之间的界面的配合接合区域的除外。 将聚合物材料施加到基底或器件的结合区域。 将该装置放置在基板上，使得聚合物材料桥接基板和装置的配合结合区域。 当聚合物材料固化时，表面张力将其拉入由聚合物掩模限定的基底和装置的配合结合区域限定的垂直柱中，并将匹配粘结区域直接对准彼此。 一旦固化，聚合物形成机械结合，并且取决于聚合物材料在基材和装置之间形成电，热和/或光学连接。