公开(公告)号：US06221514B1

公开(公告)日：2001-04-24

申请号：US09385051

申请日：1999-08-30

Applicant: Kevin Joseph Hawes ,  David Jay Vess ,  Dwadasi Hare Rama Sarma ,  Bradley Howard Carter ,  Jerome Anthony Schneider

Inventor： Kevin Joseph Hawes ,  David Jay Vess ,  Dwadasi Hare Rama Sarma ,  Bradley Howard Carter ,  Jerome Anthony Schneider

IPC: B32B1502

CPC classification number: H05K1/0265 ,  B23K35/0222 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/262 ,  H05K1/09 ,  H05K3/1225 ,  H05K3/245 ,  H05K2201/0215 ,  H05K2203/043 ,  Y10S428/901 ,  Y10S428/931 ,  Y10T428/12014 ,  Y10T428/12708 ,  Y10T428/12715

Abstract: A method by which a conventional circuit trace (14) is modified with a layer (16) of high-conductivity solder alloy to yield a high-current circuit trace (12) for high-current routing on a substrate (10). The method generally entails the use of a solder composition that contains a dispersion of metal particles (18) in a solder alloy (20). The metal particles (18) are selected on the basis of having a higher electrical conductivity than the solder alloy (20), and are present in sufficient amounts so that the electrical conductivity of the solder composition is significantly higher than that of the solder alloy (20). The solder composition is deposited on a conductor (14), and then reflowed to form a conductive layer (16) on the conductor (14). The metal particles (18) remain as a discrete dispersion within the conductive layer (16) in order to suitably promote the conductivity of the layer (16). The solder composition is preferably deposited in an amount sufficient to increase the current-carrying capacity of the resulting circuit trace (12) for high-current routing on the substrate (10), e.g., in excess of six amps.

Abstract translation: 常规电路迹线（14）用高导电性焊料合金的层（16）修饰以产生用于衬底（10）上的大电流布线的高电流电路迹线（12）的方法。 该方法通常需要使用包含金属颗粒（18）在焊料合金（20）中的分散体的焊料组合物。 基于具有比焊料合金（20）更高的导电性来选择金属颗粒（18），并且以足够的量存在，使得焊料组合物的电导率显着高于焊料合金的导电性（ 20）。 焊料组合物沉积在导体（14）上，然后回流以在导体（14）上形成导电层（16）。 为了适当地促进层（16）的导电性，金属颗粒（18）保持为导电层（16）内的离散分散体。 焊料组合物优选以足以增加所得到的电路迹线（12）的载流能力的量沉积，用于在衬底（10）上的高电流布线，例如超过6安培。

公开(公告)号：US06188582B1

公开(公告)日：2001-02-13

申请号：US09215802

申请日：1998-12-18

Applicant: Geoffrey Peter

Inventor： Geoffrey Peter

IPC: H05K118

CPC classification number: H05K3/3442 ,  H01L23/3733 ,  H01L2924/0002 ,  H05K2201/0215 ,  H05K2201/0281 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00

Abstract: A flexible integrated circuit mounting apparatus and method for mounting a chip on a printed circuit board directed to the reduction of stresses within the mounting or interconnection medium, caused principally by a mismatch of the coefficient of thermal expansion between the chip circuit and the printed circuit board, and thus reduction of the likelihood of interconnection failure between the chip and the particular surface or device to which an interconnection is made.

Abstract translation: 一种柔性集成电路安装装置和方法，用于将芯片安装在印刷电路板上，以减少安装或互连介质内的应力，主要由于芯片电路和印刷电路板之间的热膨胀系数的失配 ，从而降低芯片与形成互连的特定表面或设备之间的互连故障的可能性。

公开(公告)号：US5312576B1

公开(公告)日：2000-04-18

申请号：US70498391

申请日：1991-05-24

Applicant: WORLD PROPERTIES INC

Inventor： SWEI GWO S ,  ARTHUR DAVID J

IPC: B29C41/28 ,  B29D7/01 ,  C08J3/00 ,  C08J3/215 ,  C08J9/26 ,  H05K1/03 ,  H05K1/05 ,  H05K3/38 ,  B29C39/00 ,  B32B27/00

CPC classification number: C08J9/26 ,  B29C41/28 ,  B29D7/01 ,  B29K2027/18 ,  B29K2105/04 ,  B29K2105/16 ,  B29K2995/0006 ,  C08J3/005 ,  C08J3/215 ,  C08J2327/12 ,  H05K1/034 ,  H05K1/0373 ,  H05K1/056 ,  H05K3/386 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0239 ,  Y02P20/582

公开(公告)号：US5886415A

公开(公告)日：1999-03-23

申请号：US786615

申请日：1997-01-17

Applicant: Masatoshi Akagawa

Inventor： Masatoshi Akagawa

IPC: H01L21/60 ,  H01L23/498 ,  H01L23/532 ,  H05K1/03 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H01L23/29 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58

CPC classification number: H01L24/31 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5328 ,  H01L24/28 ,  H01L24/83 ,  H05K3/4617 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29355 ,  H01L2224/81903 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L24/12 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0373 ,  H05K2201/0215 ,  H05K3/323 ,  H05K3/4084 ,  H05K3/4647

Abstract: An anisotropic conductive sheet material includes a resin and conductive fillers, such as metallic particles, added in the resin. A conductive layer is formed on one of the surfaces of the anisotropic conductive sheet material. A circuit board includes a substrate having first and second surfaces and a circuit pattern being formed on the first surface of the substrate, an anisotropic conductive sheet having first and second surfaces, a circuit pattern being formed on the first surface thereof. The second surface of the anisotropic conductive sheet is adhered to the first surface of the substrate in such a manner that the circuit patterns are electrically connected to each other by means of the anisotropic conductive sheet. An electrically insulative layer formed on the first surface of the anisotropic conductive sheet to cover the circuit pattern thereof, except that external connecting portions thereof are exposed.

公开(公告)号：US5675889A

公开(公告)日：1997-10-14

申请号：US474343

申请日：1995-06-07

Applicant: John Acocella ,  Donald Ray Banks ,  Joseph Angelo Benenati ,  Thomas Caulfield ,  John Saunders Corbin, Jr. ,  Karl Grant Hoebener ,  David P. Watson

Inventor： John Acocella ,  Donald Ray Banks ,  Joseph Angelo Benenati ,  Thomas Caulfield ,  John Saunders Corbin, Jr. ,  Karl Grant Hoebener ,  David P. Watson

IPC: B23K1/00 ,  H01L21/48 ,  H01L23/488 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H05K3/36 ,  H05K3/42

CPC classification number: B23K1/0008 ,  B23K1/0016 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/114 ,  H05K3/3436 ,  H05K3/3478 ,  B23K2201/36 ,  B23K2201/40 ,  B23K2201/42 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2924/00013 ,  H01L2924/09701 ,  H05K2201/0215 ,  H05K2201/10234 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/0195 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0455 ,  H05K2203/082 ,  H05K3/3452 ,  H05K3/42 ,  H05K3/429 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: Two substrates are produced each with a planar, mirror-image matrix of metal contacts in a surface wiring layer. The substrates are positioned with the matrices in parallel confrontation which defines pairs of confronting contacts. A metal ball is positioned between each pair of contacts with a respective volume of joining material between the ball and each of the two respective contacts. The volumes of joining material are simultaneously melted to allow surface tension to align the substrates and to accurately center the balls between each respective pairs of contacts in a plane defines by the matrix of balls.

Abstract translation: 制造两个基板，每个基板在表面布线层中具有金属触点的平面的镜像矩阵。 衬底被定位成与平行对置的矩阵定义成对的面对的接触。 金属球被定位在每对触点之间，在球与两个相应的触头中的每一个之间具有相应体积的接合材料。 同时熔化接合材料的体积以允许表面张力对准衬底并且在由球的矩阵限定的平面中的每个相应的触头对之间精确地定位球。

公开(公告)号：US5573859A

公开(公告)日：1996-11-12

申请号：US523449

申请日：1995-09-05

Applicant: Anthony B. Suppelsa

Inventor： Anthony B. Suppelsa

IPC: B22F1/02 ,  B23K35/02 ,  B23K35/14 ,  H05K3/34 ,  B22F7/04

CPC classification number: H05K3/3484 ,  B22F1/025 ,  B23K35/0244 ,  B23K35/025 ,  H05K2201/0215 ,  H05K2201/0218 ,  H05K2201/083 ,  H05K2203/101 ,  H05K2203/104 ,  H05K3/3463 ,  H05K3/3494 ,  Y10T428/12028 ,  Y10T428/12063 ,  Y10T428/12132

Abstract: A soldering composition is self melting and is auto-regulating. The solder composition (100) has a central core (102) made from a non-magnetic metal. A coating (105) of a magnetic material surrounds most or all of the central core. A solder layer (108) overlies the coating of magnetic material, and the solder layer has a melting temperature that is lower than the Curie temperature of the magnetic material. The auto-regulating temperature substantially corresponds to the Curie temperature. When the solder composition is placed in a field of alternating current, the magnetic material heats up and melts the solder coating. When the Curie temperature is reached, the magnetic material stops heating, thus controlling the maximum temperature of the soldering composition. As the temperature of the composition drops below the Curie temperature, the magnetic material again heats up, thus keeping the temperature of the solder constant.

Abstract translation: 焊接组合物是自熔的并且是自动调节的。 焊料组合物（100）具有由非磁性金属制成的中心芯（102）。 磁性材料的涂层（105）围绕中心芯的大部分或全部。 焊料层（108）覆盖在磁性材料的涂层上，焊料层的熔化温度低于磁性材料的居里温度。 自动调节温度基本上对应于居里温度。 当焊料组合物置于交流电场中时，磁性材料加热并熔化焊料涂层。 当达到居里温度时，磁性材料停止加热，从而控制焊接组合物的最高温度。 随着组合物的温度低于居里温度，磁性材料再次升温，从而保持焊料的温度恒定。

公开(公告)号：US5393568A

公开(公告)日：1995-02-28

申请号：US160428

申请日：1993-11-30

Applicant: Thomas J. Valente ,  Henri J. A. Charmasson

Inventor： Thomas J. Valente ,  Henri J. A. Charmasson

IPC: B05D3/08 ,  B05D5/06 ,  C09D5/16 ,  C09D5/38 ,  C23C24/08 ,  H01B1/22 ,  H01B3/00 ,  H05K1/03 ,  H05K3/28 ,  H05K3/46 ,  B05D3/10

CPC classification number: H01B3/006 ,  B05D3/08 ,  B05D5/067 ,  C09D5/1618 ,  C09D5/38 ,  C23C24/08 ,  H01B1/22 ,  H05K1/0373 ,  H05K3/285 ,  H05K2201/0215 ,  H05K2203/0315 ,  H05K2203/1316 ,  H05K3/4641

Abstract: A cold process for laying a textured or polished coat of bronze, copper, brass, pewter or other metallic substance over a mineral or organic surface comprises the step of mixing a sintering metal powder with a polyester resin and a ketonic catalyst for forming a spreadable, moldable or sprayable paste that hardens to a coat having essentially the mechanical and chemical characteristics of the selected metallic substance, but exhibiting no electrical conductivity.

Abstract translation: 用于在矿物或有机表面上铺设纹理或抛光的青铜，铜，黄铜，锡或其他金属物质的冷加工方法包括将烧结金属粉末与聚酯树脂和酮催化剂混合以形成可铺展的， 可模制或可喷涂的糊剂，其硬化到具有基本上所选金属物质的机械和化学特性但不显示导电性的涂层。

公开(公告)号：US5374453A

公开(公告)日：1994-12-20

申请号：US90488

申请日：1993-07-13

Applicant: Gwo S. Swei ,  David J. Arthur

Inventor： Gwo S. Swei ,  David J. Arthur

IPC: B29C41/28 ,  B29D7/01 ,  C08J3/00 ,  C08J3/215 ,  C08J9/26 ,  H05K1/03 ,  H05K1/05 ,  H05K3/38 ,  B05D3/02

CPC classification number: C08J9/26 ,  B29C41/28 ,  B29D7/01 ,  C08J3/005 ,  C08J3/215 ,  H05K1/034 ,  H05K1/0373 ,  B29K2027/18 ,  B29K2105/04 ,  B29K2105/16 ,  C08J2327/12 ,  H05K1/056 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0239 ,  H05K3/386 ,  Y02P20/582

Abstract: A method for making a particulate filled polymeric matrix composite film includes mixing a polymeric matrix material with a dispersion of particulate filler in a carrier liquid to form a casting composition and adjusting the viscosity of the casting composition to retard separation of the particulate filler from the composition. A layer of the viscosity-adjusted casting composition is cast on a substrate and the layer is consolidated to form the particulate filled polymer matrix composite film. Films made by the method include very thin, e.g less than 1.0 mil, fluoropolymeric matrix films highly filled with very small diameter, preferably spherical, particles for use as, e.g. dielectric substrate materials in laminar electrical circuits.

Abstract translation: 制备颗粒填充的聚合物基质复合膜的方法包括将聚合物基体材料与颗粒填料的分散体混合在载体液体中以形成流延组合物并调节流延组合物的粘度以阻止颗粒填料与组合物的分离 。 将粘度调节的浇铸组合物的一层浇铸在基材上，并将该层固结以形成填充颗粒的聚合物基质复合膜。 通过该方法制备的膜包括非常薄的，例如小于1.0密耳的高度填充有非常小直径，优选球形的颗粒的含氟聚合物基质膜，用于例如， 层状电路中的电介质基片材料。

公开(公告)号：US5294477A

公开(公告)日：1994-03-15

申请号：US796309

申请日：1991-11-22

Applicant: Seiji Kanba ,  Nobuyuki Wada ,  Harunobu Sano ,  Hiroshi Takagi

Inventor： Seiji Kanba ,  Nobuyuki Wada ,  Harunobu Sano ,  Hiroshi Takagi

IPC: H05K1/02 ,  H01L23/14 ,  H01L23/373 ,  H05K1/03 ,  B32B9/00

CPC classification number: H05K1/0306 ,  H01L23/142 ,  H01L23/3733 ,  H05K1/03 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2201/0215 ,  Y10T428/24942 ,  Y10T428/24983 ,  Y10T428/252 ,  Y10T428/256

Abstract: A functionally gradient circuit board is constituted by a mixture of a metal and an insulating ceramic composition, the abundance ratio of the metal component to the component of the insulating ceramic composition being changed in the direction of thickness of the board.

Abstract translation: 功能梯度电路板由金属和绝缘陶瓷组合物的混合物构成，金属组分与绝缘陶瓷组合物的组分的丰度比在板的厚度方向上改变。

公开(公告)号：US5170931A

公开(公告)日：1992-12-15

申请号：US644528

申请日：1991-01-23

Applicant: Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

Inventor： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

IPC: H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H01L25/50 ,  H01L23/4985 ,  H01L23/5385 ,  H05K3/3478 ,  H05K3/363 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15321 ,  H05K1/141 ,  H05K2201/0215 ,  H05K2201/049 ,  H05K2201/10234 ,  H05K2201/10477 ,  H05K2201/10681 ,  H05K2201/10734 ,  H05K2201/10984 ,  H05K2203/0165 ,  H05K2203/0278 ,  H05K2203/041 ,  H05K2203/0557

Abstract: Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package. The resulting electronic packaging structure includes electrically conductive spacers, such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding bonding pads on the second level electronic package, and which physically support the flexible film of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture comprising a base plate, a pressure insert with a resilient member, and a top plate. The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled, leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired. The spacers may be attached to the flexible film semiconductor chip carrier using a special template having a pattern of openings corresponding to the pattern of outer lead bonding pads on the flexible film semiconductor chip carrier.