公开(公告)号：US07027308B2

公开(公告)日：2006-04-11

申请号：US10444989

申请日：2003-05-27

Applicant: Jin-Kwon Park ,  Chan-youn Won

Inventor： Jin-Kwon Park ,  Chan-youn Won

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0246 ,  H01R12/721 ,  H01R13/658 ,  H05K1/0231 ,  H05K1/14 ,  H05K7/1429 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10189 ,  H05K2201/1053

Abstract: A PCB having a card slot receiving a card provided with signal input/output pins and a circuit element to provide extended capability is inserted, and having data transmission pins, a power pin and a ground pin in correspondence to the signal input/output pins, comprises an electronic device internally provided for impedance matching with the card, and having a first end connected to one of the data transmission pins and a second end connected to one of the power pin and the ground pin. With this configuration, a card slot internally comprises an electronic device for impedance matching, so that a space of the PCB can be efficiently utilized.

Abstract translation: 插入具有接收设置有信号输入/输出引脚的卡的卡插槽和提供扩展能力的电路元件的PCB，并且具有对应于信号输入/输出引脚的数据传输引脚，电源引脚和接地引脚， 包括内部提供用于与卡的阻抗匹配的电子设备，并且具有连接到数据传输引脚之一的第一端和连接到电源引脚和接地引脚之一的第二端。 利用这种配置，卡槽内部包括用于阻抗匹配的电子设备，从而可以有效地利用PCB的空间。

公开(公告)号：US20060024984A1

公开(公告)日：2006-02-02

申请号：US11173927

申请日：2005-07-01

Applicant: Thomas Cohen ,  Marc Cartier ,  Mark Gallus

Inventor： Thomas Cohen ,  Marc Cartier ,  Mark Gallus

IPC: H01R12/00

CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

公开(公告)号：US06963941B1

公开(公告)日：2005-11-08

申请号：US09583883

申请日：2000-05-31

Applicant: Terry R. Lee

Inventor： Terry R. Lee

IPC: G06F13/00 ,  G06F13/40 ,  H05K1/14

CPC classification number: G06F13/4095 ,  H05K1/14 ,  H05K1/145 ,  H05K2201/044

Abstract: A high-speed short-loop bus topology that routes the bus into a first expansion connector and out of a first expansion card inserted within the connector is disclosed. The bus is not routed out of the first expansion connector. Instead, the bus is routed from the first expansion card into a second expansion card by a jumper mechanism. The bus is routed through the second expansion card and out of a second expansion connector housing the second expansion card, where the bus can be terminated or routed into another expansion connector having another expansion card. By routing the bus in this manner, it is shorter than prior art buses found in loop-through bus systems and capable of substantially maintaining a uniform transmission line impedance. Moreover, the operating bandwidth of the short-loop bus is increased since the bus is short and does not have stubs or signal reflections.

Abstract translation: 公开了一种高速短路总线拓扑，其将总线路由到插入在连接器内的第一扩展连接器和第一扩展卡中。 总线不会从第一个扩展连接器路由出来。 相反，总线通过跳线机制从第一扩展卡路由到第二扩展卡。 总线通过第二扩展卡路由出第二个扩展连接器，第二扩展连接器容纳第二个扩展卡，其中总线可以被终止或路由到具有另一个扩展卡的另一个扩展连接器中。 通过以这种方式路由总线，它比在环通总线系统中发现的现有技术总线更短，并且能够基本上保持均匀的传输线阻抗。 此外，短路总线的工作带宽增加，因为总线短路并且没有短线或信号反射。

公开(公告)号：US20050226076A1

公开(公告)日：2005-10-13

申请号：US10907420

申请日：2005-03-31

Applicant: Ryan Petersen

Inventor： Ryan Petersen

IPC: G06F1/26 ,  G11C5/00 ,  G11C5/14 ,  H05K1/02 ,  H05K1/14

CPC classification number: G06F1/26 ,  G11C5/147 ,  H05K1/0231 ,  H05K1/141 ,  H05K2201/044

Abstract: An apparatus for buffering power transients in a supply power for expansion cards inserted into expansion slots on a computer motherboard. The apparatus comprises a printed circuit board, a connector on the printed circuit board, and at least one capacitor on the printed circuit board. The connector is configured to fit into one of the expansion slots on the motherboard, and comprises at least one power pin and at least one ground pin. The at least one capacitor is connected to the power and ground pins of the connector and has sufficient capacitance to buffer power transients within the supply power to the expansion slots.

Abstract translation: 一种用于缓冲插入到计算机主板上的扩展槽中的扩展卡的供电电源瞬态的装置。 该装置包括印刷电路板，印刷电路板上的连接器和印刷电路板上的至少一个电容器。 连接器被配置成装配到主板上的一个扩展槽中，并且包括至少一个电源引脚和至少一个接地引脚。 至少一个电容器连接到连接器的电源和接地引脚，并且具有足够的电容以缓冲对扩展槽的供电的功率瞬变。

公开(公告)号：US06940730B1

公开(公告)日：2005-09-06

申请号：US10636365

申请日：2003-08-07

Applicant: Robin Berg, Jr. ,  Todd Husom ,  Derek Sayres

Inventor： Robin Berg, Jr. ,  Todd Husom ,  Derek Sayres

IPC: H04Q1/02 ,  H04Q1/10 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K7/14 ,  H05K7/18

CPC classification number: H04Q1/10 ,  H04Q1/023 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/116 ,  H04Q2201/06 ,  H04Q2201/10 ,  H04Q2201/12 ,  H05K1/0216 ,  H05K1/14 ,  H05K1/18 ,  H05K7/1425 ,  H05K7/186 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/09663

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.

Abstract translation: 公开了一种底盘和相关通信电路卡。 底盘具有散热和阻燃特征，同时容纳高密度的电路卡。 实施例包括具有双层中间层的内壳，其将底盘分成顶部和底部室。 每个层具有部分对准的槽，并且在两层之间提供气隙。 实施例还包括在两个网格层之间具有气隙的双层网状覆盖物。 在内壳体的内表面上设置突起和凹槽，以接收在一个边缘上具有引导件的电路卡和另一边缘上的翅片。 电路卡包括导体结构，例如具有配对和分离的导体的多个板层。 电路卡还包括定位成与底盘的通风特征配合的一些组件，并且包括一些选择用于低功耗或降低可燃性的组件。

公开(公告)号：US20050170673A1

公开(公告)日：2005-08-04

申请号：US11019674

申请日：2004-12-23

Applicant: Jung-hwan Choi

Inventor： Jung-hwan Choi

IPC: G06F13/16 ,  G06F12/00 ,  G06F12/04 ,  G06F12/06 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  H01R12/00 ,  H05K1/02 ,  H05K1/14

CPC classification number: G06F13/409 ,  G06F13/4243 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0274 ,  H05K1/14 ,  H05K2201/044

Abstract: The memory module includes a plurality of memory devices, a first connector and a second connector. The first connector is disposed at a first position on the memory module. The first connector is configured to carry low-speed signals for the memory devices. The second connector is disposed at a second position on the memory module, different from the first position. The second connector is configured to carry high-speed signals for at least one of the memory devices. The high-speed signals are a higher speed form of signaling than the low-speed signals. The memory system may include at least one slot electrically connected to a chip set and at least one memory module electrically connected to the slot via the first connector. A transmission line such as a fiber optic cable electrically connects the second connector and the chip set.

Abstract translation: 存储器模块包括多个存储器件，第一连接器和第二连接器。 第一连接器设置在存储器模块的第一位置。 第一个连接器被配置为携带用于存储器件的低速信号。 第二连接器设置在与第一位置不同的存储器模块的第二位置。 第二连接器被配置为承载至少一个存储器件的高速信号。 高速信号是比低速信号更高速的信号形式。 存储器系统可以包括电连接到芯片组的至少一个槽和经由第一连接器电连接到槽的至少一个存储器模块。 诸如光纤电缆的传输线电连接第二连接器和芯片组。

公开(公告)号：US20050136703A1

公开(公告)日：2005-06-23

申请号：US10742501

申请日：2003-12-19

Applicant: Koenraad Van Schuylenbergh ,  Armin Volkel ,  Thomas DiStefano ,  Michel Rosa ,  David Fork ,  Eugene Chow ,  Meng Lean

Inventor： Koenraad Van Schuylenbergh ,  Armin Volkel ,  Thomas DiStefano ,  Michel Rosa ,  David Fork ,  Eugene Chow ,  Meng Lean

IPC: H05K1/14 ,  H01B11/00 ,  H01R12/00 ,  H01R12/04 ,  H05K3/32 ,  H05K3/36

CPC classification number: H01R12/78 ,  H05K1/147 ,  H05K3/323 ,  H05K3/361 ,  H05K3/365 ,  H05K2201/044 ,  H05K2201/09845

Abstract: A data transmission interconnect assembly (e.g., a router) capable of transmission speeds in excess of 40 Gbps in which a line-card is detachably coupled to a backplane using flexible flat cables that are bent to provide a continuous, smooth curve between the connected boards, and connected by a connection apparatus that employs cable-to-cable interface members that are transparent to the transmitted signal waves. Microspring contact structures are formed on the cables, or on a contact structure pressed against the cables, to provide interface arrangements that are smaller than a wavelength of the transmitted signal. A connector apparatus uses a cam mechanism to align the cables, and then to press a contact structure, having micro spring interface members formed thereon, against the cables. An alterative contact structure uses anisotropic conductive film.

公开(公告)号：US20040246064A1

公开(公告)日：2004-12-09

申请号：US10850427

申请日：2004-05-21

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Junichi Abe ,  Yuichirou Murata

IPC: H01P003/08 ,  H01P005/02

CPC classification number: H01P3/088 ,  H05K1/0237 ,  H05K1/113 ,  H05K1/114 ,  H05K1/14 ,  H05K3/366 ,  H05K2201/044 ,  H05K2201/10189

Abstract: A multilayer circuit board for high-frequency signals includes: a multilayer wiring board unit including, at least one wiring layer, one or more ground layers configured by a conductive material, insulating layers between the layers, and a first external electrode electrically connected to a transmission line on an episurface; and a connector unit including a second external electrode electrically connected to the first external electrode, and a fitting portion for holding on the multilayer wiring board unit an external circuit board or an external connector. The distance d between the first external electrode (7) and the ground layer perpendicularly below and most closely disposed to the first external electrode is determined within the range dlnulldnulldu with respect to the values dl and du defined based on tolerance of the impedance nullZ.

Abstract translation: 一种用于高频信号的多层电路板包括：多层布线板单元，包括：至少一个布线层，由导电材料构成的一个或多个接地层，所述层之间的绝缘层和与第一外部电极电连接的第一外部电极 传输线在一个情节; 以及连接器单元，包括与第一外部电极电连接的第二外部电极，以及用于在多层布线板单元上保持外部电路板或外部连接器的装配部分。 在第一外部电极（7）和垂直于第一外部电极最接近地设置的接地层之间的距离d在相对于基于公差的d 1和 阻抗DeltaZ。

公开(公告)号：US20040239438A1

公开(公告)日：2004-12-02

申请号：US10449215

申请日：2003-05-30

Inventor： John R. Benham ,  John L. Critchlow ,  Tao Liang

IPC: H01P005/12

CPC classification number: G06F13/4086 ,  H01P5/185 ,  H05K1/0239 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/10189

Abstract: A compact electromagnetic coupler for use with digital transmission system is described. In one embodiment, the apparatus includes a first transmission structure, including a portion having a geometry. A second transmission structure having the geometry and positioned proximate the portion of the first transmission line structure having the geometry to form a compact electromagnetic coupler with the first transmission structure a geometry of the electromagnetic coupler to enable placement within a footprint of a standard card connector. The compact electromagnetic coupler so formed enables reconstruction of the logical state and timing of a signal transmitted along the first transmission structure.

Abstract translation: 描述了一种用于数字传输系统的小型电磁耦合器。 在一个实施例中，该装置包括第一传输结构，其包括具有几何形状的部分。 第二传输结构具有几何形状并且靠近第一传输线结构的具有几何形状的部分定位，以形成具有第一传输结构的小型电磁耦合器，该电磁耦合器的几何形状能够放置在标准卡连接器的覆盖区内。 这样形成的小型电磁耦合器能够重建沿着第一传输结构传输的信号的逻辑状态和定时。

公开(公告)号：US20040090757A1

公开(公告)日：2004-05-13

申请号：US10685605

申请日：2003-10-16

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Yuichiro Murata

IPC: H05K007/02 ,  H05K007/06 ,  H05K007/08 ,  H05K007/10

CPC classification number: H05K1/0248 ,  H05K1/0245 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10189

Abstract: On the surface of a back board 30 are provided outermost-layer signal lines 6a, 6b, each having a length different form each other on the basis of the difference in length between connector lines 3a, 3b, and these outermost-layer signal lines are connected with the connector lines 3a, 3b, respectively. A digital signal nullanull generated in the circuit of a daughter board 10 reaches a through hole 2a through an internal-layer signal line 1a traced within the internal layer of the daughter board 10, and is further transmitted to an internal-layer signal line 5a of the back board 30 through the connector line 3a, the outermost-layer signal line 6a, and a through hole 4a. The digital signal nullanull is further transmitted to an internal-layer signal line nullanull via a through hole 4anull, a connector line 3anull, and a through hole 2anull.

Abstract translation: 在背板30的表面上设置最外层信号线6a，6b，其最大层信号线6a，6b的长度根据连接线3a，3b之间的长度差彼此不同，并且这些最外层信号线是 分别与连接线3a，3b连接。 在子板10的电路中产生的数字信号“a”通过跟踪在子板10的内层内的内层信号线1a到达通孔2a，并进一步传输到内层信号线 通过连接器线3a，最外层信号线6a和通孔4a的背板30的5a。 数字信号“a”经由通孔4a'，连接器线3a'和通孔2a'进一步传输到内层信号线“a”。