公开(公告)号：US6010769A

公开(公告)日：2000-01-04

申请号：US875093

申请日：1997-07-16

Applicant: Kenji Sasaoka ,  Hiroshi Odaira ,  Madoka Fujiwara ,  Fumitoshi Ikegaya ,  Takahiro Mori

Inventor： Kenji Sasaoka ,  Hiroshi Odaira ,  Madoka Fujiwara ,  Fumitoshi Ikegaya ,  Takahiro Mori

IPC: H01L21/48 ,  H01L23/538 ,  H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/17 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K3/4652 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/095 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/09863 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conductive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic elements, etc.

Abstract translation: PCT No.PCT / JP96 / 03378 Sec。 371日期1997年7月16日 102（e）日期1997年7月16日PCT 1996年11月18日PCT公布。 第WO97 / 19579号公报 日期1997年5月29日一种使用导电柱的多层布线板用于布线层的互连。 由于通孔在多层布线板的布线层的通孔焊盘中钻孔，所以在将导电柱连接到通孔焊盘时，可以释放在导电柱和布线层之间施加的应力。 由于每个导电柱的外侧面在导电柱和通孔焊盘之间的接触部处平滑地延续到通路接合面的表面，所以能够消除切口效果。 因此，即使在制造多层布线基板期间对连接件施加应力并且安装电子元件等时也确保互连的可靠性。

公开(公告)号：US5603981A

公开(公告)日：1997-02-18

申请号：US419543

申请日：1995-04-10

Applicant: Kaoru Hashimoto ,  Tatsuo Chiyonobu ,  Kyoichiro Kawano ,  Kouji Watanabe

Inventor： Kaoru Hashimoto ,  Tatsuo Chiyonobu ,  Kyoichiro Kawano ,  Kouji Watanabe

IPC: H01R13/03 ,  H01L21/48 ,  H01L23/498 ,  H01R24/00 ,  H01R43/00 ,  H01R43/16 ,  H05K3/34 ,  B05D5/12 ,  B23K31/02 ,  H01R43/02

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49866 ,  H05K3/3436 ,  H05K3/3463 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01322 ,  H05K2201/0373 ,  H05K2201/09863 ,  H05K2203/0594 ,  H05K2203/1105 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49204 ,  Y10T29/49215

Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.

Abstract translation: 一种电连接装置，包括在其上设置有输入/输出端子的第一电路板，每个端子具有涂覆有镓的尖端表面和在其上设置有接触端子的第二电路板，每个端子具有涂覆有铟的尖端表面 或锡。 当第一电路板的输入/输出端子与第二电路板的各个端子接触并且彼此电连接时，通过镓和铟或锡之间的相互作用形成低熔点合金层。 第二金属层包括大致垂直于端子表面延伸的多个线状金属支撑体和由线状金属支撑体保持的低熔点金属。

公开(公告)号：US20240074062A1

公开(公告)日：2024-02-29

申请号：US18355527

申请日：2023-07-20

Applicant: CARUX TECHNOLOGY PTE. LTD.

Inventor： Hsin-Fa HSU ,  Yu-Ling HUNG ,  Hsien-Yao HSIAO ,  Tsu-Hsien KU

IPC: H05K1/18 ,  H05K3/28 ,  H05K3/30

CPC classification number: H05K1/181 ,  H05K3/28 ,  H05K3/301 ,  H05K2201/09863

Abstract: An electronic device is provided, including an electronic element, and a protective substrate. The protective substrate includes a concave portion, and a flat portion. The concave portion has a concave surface and a convex surface that is opposite to the concave surface. The flat portion is connected to the concave portion. The electronic element overlaps the concave portion and is arranged under the convex surface.

公开(公告)号：US20170196096A1

公开(公告)日：2017-07-06

申请号：US15398935

申请日：2017-01-05

Applicant: IBIDEN CO., LTD.

Inventor： Teruyuki ISHIHARA ,  Ayumi SHIBATA ,  Kosuke IKEDA

IPC: H05K3/46 ,  H05K1/18 ,  H05K3/06 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K3/4682 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K3/0035 ,  H05K3/0097 ,  H05K3/061 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2201/04 ,  H05K2201/09863 ,  H05K2203/1536

Abstract: A printed wiring board includes a resin insulating layer, a projecting conductor layer formed on a surface of the resin insulating layer such that the projecting conductor layer is projecting from the surface of the resin insulating layer, and an integral conductor structure formed in the resin insulating layer and including a via conductor portion and an embedded conductor layer portion such that the embedded conductor layer portion is embedded in the resin insulating layer on the opposite side of the resin insulating layer with respect to the projecting conductor layer and has an exposed surface exposed from the resin insulating layer and the via conductor portion is formed through the resin insulating layer and is connecting the embedded conductor layer portion and projecting conductor layer. The projecting conductor layer and integral conductor structure are formed such that the projecting conductor layer and integral conductor structure are individual conductor structures.

公开(公告)号：US20170019996A1

公开(公告)日：2017-01-19

申请号：US15124499

申请日：2015-02-27

Applicant: SONY CORPORATION

Inventor： Toshihiko WATANABE

IPC: H05K1/11 ,  H05K3/34 ,  H05K3/40 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/116 ,  H01L21/486 ,  H01L23/49827 ,  H01L33/48 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1531 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/3489 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09154 ,  H05K2201/0959 ,  H05K2201/09863 ,  H05K2201/10106 ,  H05K2201/10484 ,  H05K2203/1383 ,  H05K2203/1394 ,  Y02P70/613

Abstract: A mounting substrate includes a through-hole 13 formed in a substrate 10, a first land part 21, a second land part 31, a first component attaching part 22, a second component attaching part 32, a conductive layer 14, and a filling member 15 filled into a part of the through-hole 13. A shortest distance allowable value L0 from the center of the first land part 21 to a component 51 is determined on the basis of the volume Vh of a part of the through-hole 15 positioned above a top surface of the filling member 15 on the side of the first land part 21, the length L1 of the component 51 to be mounted to the first component attaching part 22, and the maximum allowable value of the inclination of the component 51 to be mounted to the first component attaching part 22 relative to the first surface 11 of the substrate 10.

Abstract translation: 安装基板包括形成在基板10中的通孔13，第一接地部21，第二接地部31，第一部件安装部22，第二部件安装部32，导电层14和填充部件 15被填充到通孔13的一部分中。从第一陆部21的中心到部件51的最短距离允许值L0基于定位的通孔15的一部分的体积Vh来确定 在第一接地部21侧的填充部件15的上表面上，要安装到第一部件安装部22的部件51的长度L1和部件51的倾斜度的最大允许值为 相对于基板10的第一表面11安装到第一部件安装部22。

公开(公告)号：US09532452B2

公开(公告)日：2016-12-27

申请号：US14607199

申请日：2015-01-28

Applicant: LG INNOTEK CO., LTD.

Inventor： Jeong Won Park ,  Hee Beom An ,  Kyu Dong Kang ,  Gyu Ho Park ,  Su Jin Park ,  Sang Hoon Yoon

IPC: H05K1/11 ,  H05K1/03

CPC classification number: H05K1/115 ,  H05K1/0366 ,  H05K2201/09863

Abstract: A printed circuit board includes a substrate; and a hole passing through first and second surfaces of the substrate. The hole includes an area in which a width of the hole formed in an inner side of the substrate is formed larger than that of an opening formed on the first surface and/or the second surface.

Abstract translation: 印刷电路板包括基板; 以及穿过基板的第一和第二表面的孔。 孔包括形成在基板的内侧的孔的宽度形成为大于形成在第一表面和/或第二表面上的开口的宽度的区域。

公开(公告)号：US09451711B2

公开(公告)日：2016-09-20

申请号：US14169314

申请日：2014-01-31

Applicant: IBIDEN CO., LTD.

Inventor： Toshiaki Hibino

IPC: H05K1/03 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

CPC classification number: H05K3/429 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/0032 ,  H05K3/0055 ,  H05K3/108 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2201/09827 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/2072 ,  H05K2203/108 ,  H05K2203/1476

Abstract: A printed wiring board includes an insulating substrate having a penetrating hole formed through the substrate, a first conductive pattern formed on first surface of the substrate, a second conductive pattern formed on second surface of the substrate on the opposite side of the first surface, and a through-hole conductor formed in the penetrating hole in the substrate such that the conductor is connecting the first conductive pattern on the first surface of the substrate and the second conductive pattern on the second surface of the substrate. The penetrating hole has a first opening portion opening on the first surface of the substrate, a second opening portion opening on the second surface of the substrate and a third opening portion connecting the first and second opening portions, and the third opening portion has the maximum diameter which is greater than the minimum diameters of the first and second opening portions.

Abstract translation: 印刷布线板包括：绝缘基板，具有穿过该基板形成的贯通孔，形成在基板的第一面上的第一导体图案，形成在基板的与第一面相反一侧的第二面上的第二导电图案;以及 形成在所述基板的所述贯通孔中的通孔导体，使得所述导体将所述基板的第一表面上的所述第一导电图案与所述基板的所述第二表面上的所述第二导电图案连接。 所述贯通孔具有在所述基板的第一面上开口的第一开口部，在所述基板的第二面上开口的第二开口部，以及连接所述第一开口部和所述第二开口部的第三开口部， 其直径大于第一和第二开口部分的最小直径。

公开(公告)号：US20160249463A1

公开(公告)日：2016-08-25

申请号：US15027774

申请日：2014-09-24

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Nobuyuki YOSHIDA

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K3/4652 ,  H05K3/0026 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0355 ,  H05K2201/0397 ,  H05K2201/09863 ,  H05K2201/2072 ,  H05K2203/1184 ,  H05K2203/1476

Abstract: The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole, an overhang of a metal foil formed at an opening of the hole, and lower space formed between the overhang and an inside wall of the hole, by using a conformal method or a direct laser method; and (2) a step of filling in the hole by forming electrolytic filling plating layers within the hole and on the metal foil, wherein the filling-in of the hole by the formation of electrolytic filling plating layers in the step (2) is carried out by temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating, and increasing it again.

Abstract translation: 本发明是一种多层布线板的制造方法，其特征在于，具有（1）具有通孔的孔，形成在所述孔的开口部的金属箔的突出部以及所述突出部和 孔的内壁，通过使用保形法或直接激光法; （2）通过在孔内和金属箔上形成电解填充镀层来填充孔的步骤，其中在步骤（2）中通过形成电解填充镀层填充孔， 通过暂时降低电解填充电镀中间的电解填充电镀的电流密度，并再次增加。

公开(公告)号：US20160242299A1

公开(公告)日：2016-08-18

申请号：US15027756

申请日：2014-09-24

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Nobuyuki YOSHIDA

IPC: H05K3/42 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K3/423 ,  H05K3/0026 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09863 ,  H05K2201/2072 ,  H05K2203/1184 ,  H05K2203/1476 ,  H05K2203/1492

Abstract: The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.

Abstract translation: 本发明是一种多层布线基板的制造方法，其特征在于，具有（1）在上层布线图案的金属箔和内层布线图案之间设置用于通路孔的工序， 直接激光法，（2）通孔形成电解填充镀层形成通孔的步骤，其中在步骤（2）中形成电解填充电镀层是通过重复变化进行的 在电解填充电镀中间暂时降低电解填充电镀电流密度的电流密度，然后在电解填充电镀层阻挡用于通孔的孔的开口之前再次增加两次或更多次。

公开(公告)号：US20160221038A1

公开(公告)日：2016-08-04

申请号：US15095264

申请日：2016-04-11

Applicant: Texas Instruments Incorporated

Inventor： PETER B. JOHNSON ,  IRA OAKTREE WYGANT

IPC: B06B1/02 ,  B81C1/00

CPC classification number: B06B1/0292 ,  B06B2201/76 ,  B81B7/007 ,  B81B2203/0127 ,  B81B2207/096 ,  B81C1/00301 ,  B81C2201/013 ,  B81C2203/036 ,  H02N1/006 ,  H04R19/005 ,  H05K2201/09845 ,  H05K2201/09863

Abstract: A Capacitive Micromachined Ultrasonic Transducer (CMUT) device including at least one CMUT element with at least one CMUT cell is formed. A patterned dielectric layer thereon including a thick and a thin dielectric region is formed on a top side of a single crystal material substrate. A second substrate is bonded to the thick dielectric region to provide at least one sealed micro-electro-mechanical system (MEMS) cavity. The second substrate is thinned to reduce a thickness of said second substrate to provide a membrane layer. The membrane layer is etched to form a movable membrane over said MEMS cavity and to remove said membrane layer over said top side substrate contact area. The thin dielectric region is removed from over said top side substrate contact area. A top side metal layer is formed including a trace portion coupling said top side substrate contact area to said movable membrane. From a bottom side surface of said first substrate, etching is performed to open an isolation trench around said single crystal material to form a through-substrate via (TSV) plug of said single crystal material at least under said top side substrate contact area which is electrically isolated from surrounding regions of said single crystal material.

Abstract translation: 形成包括至少一个具有至少一个CMUT单元的CMUT元件的电容式微加工超声波传感器（CMUT）装置。 在单晶材料基板的上侧形成有包含厚而薄的电介质区域的图案化电介质层。 第二衬底被结合到厚电介质区域以提供至少一个密封的微机电系统（MEMS）空腔。 第二衬底被薄化以减小所述第二衬底的厚度以提供膜层。 蚀刻膜层以在所述MEMS空腔上形成可移动膜，并且在所述顶侧基板接触区域上去除所述膜层。 从所述顶侧基板接触区域的上方去除薄介电区域。 形成顶侧金属层，其包括将所述顶侧基板接触区域连接到所述可动膜的迹线部分。 从所述第一衬底的底侧表面进行蚀刻以打开围绕所述单晶材料的隔离沟槽，以至少在所述顶侧衬底接触区域的下方形成所述单晶材料的贯穿衬底通孔（TSV）插头 与所述单晶材料的周围区域电隔离。