公开(公告)号：US06782615B2

公开(公告)日：2004-08-31

申请号：US09204123

申请日：1998-12-02

Applicant: Kazutaka Shibata ,  Tsunemori Yamaguchi

Inventor： Kazutaka Shibata ,  Tsunemori Yamaguchi

IPC: H05K302

CPC classification number: H05K3/323 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10727 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A plurality of electronic components having conductive connecting members are surface-mounted to a target surface of a circuit board by specifying terminal-forming areas that are each no greater than the corresponding one of the electronic components and each include at least one terminal part such that at least one of these terminal-forming areas includes a plurality of terminal parts directly and that each pair of the terminal parts within any one of the terminal-forming areas is closer to each other than any pair of the terminal parts in different ones of the terminal-forming areas. An anisotropic conductive layer is formed on this target surface so as to span these terminal-forming areas, and the plurality of electronic components are placed on this anisotropic conductive layer individually above the plurality of terminal-forming areas. As the layer is heated, these electronic components are pressed against the layer such that the conductive connecting members of the electronic components become attached to and electrically conductive with corresponding ones of the terminal parts on the circuit board. The anisotropic conductive layer remains electrically insulative elsewhere.

Abstract translation: 具有导电连接构件的多个电子部件通过规定不大于相应的一个电子部件的端子形成区域来表面安装到电路板的目标表面，并且每个端子形成区域包括至少一个端子部分，使得 这些端子形成区域中的至少一个直接包括多个端子部，并且在任一个端子形成区域内的每对端子部分彼此之间的任何一对端子部分彼此更靠近 终端形成区域。 在该目标表面上形成各向异性导电层，以跨越这些端子形成区域，并且将多个电子部件分别放置在多个端子形成区域上方的该各向异性导电层上。 当层被加热时，这些电子部件被压靠在层上，使得电子部件的导电连接部件被附接到电路板上的对应的端子部分并与其导电。 各向异性导电层在其他地方保持电绝缘。

公开(公告)号：US06781488B2

公开(公告)日：2004-08-24

申请号：US10105448

申请日：2002-03-26

Applicant: Yoshio Tsukiyama ,  Masato Shiobara

Inventor： Yoshio Tsukiyama ,  Masato Shiobara

IPC: H01P100

CPC classification number: H01P1/047 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6616 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/15313 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0243 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/09618 ,  H05K2201/10727 ,  H05K2201/10969 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A connected construction of a high-frequency package and a wiring board have an excellent high-frequency transmission characteristic without degradation of the transmission characteristic of even high-frequency signals in a wide band ranging from 20 GHz to 80 GHz in the case of connecting a high-frequency package to a wiring board. A distance between conductive vias and conductive vias to connect grounds formed on both main surfaces of a high-frequency transmission line substrate constituting the high-frequency package, and a distance between conductive vias and conductive vias to connect grounds formed on both main surfaces of the wiring board on which the high-frequency package is mounted, are set in consideration of the dielectric constant of the high-frequency transmission line substrate and the dielectric constant of the wiring board in order to improve the high-frequency transmission characteristic between the high-frequency transmission line substrate and the wiring board.

Abstract translation: 高频封装和布线板的连接结构具有优异的高频传输特性，而在连接一个高频率封装和布线板的情况下，在20GHz至80GHz范围内的宽频带内甚至高频信号的传输特性也不会降低 高频封装到接线板。 导电通孔和导电通孔之间的距离，以连接形成在构成高频封装的高频传输线基板的两个主表面上的接地，以及导电通孔和导电通孔之间的距离，以连接形成在高频封装的两个主表面上的接地 考虑到高频传输线基板的介电常数和布线板的介电常数，设置安装高频封装的布线板，以便提高高频传输线基板的高频传输特性， 频率传输线基板和布线板。

公开(公告)号：US20040161906A1

公开(公告)日：2004-08-19

申请号：US10779824

申请日：2004-02-17

Inventor： S. Kumar Khanna

IPC: H01L021/76 ,  H01L021/30 ,  H01L021/46

CPC classification number: H01L24/31 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29388 ,  H01L2224/29393 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/8322 ,  H01L2224/83222 ,  H01L2224/838 ,  H01L2224/83951 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K3/323 ,  H05K2201/0218 ,  H05K2201/083 ,  H05K2201/10727 ,  H05K2203/104 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: Conductive material or particles of an anisotropic conductive compound or material sandwiched between at least two aligned conductive contacts are vibrated mechanically, magnetically, or both mechanically and magnetically while the anisotropic conductive compound is curing. The conductive material is subjected to a static, substantially homogeneous DC magnetic field (i) before, (ii) following or (iii) at least partially during the time the conductive material is being vibrated.

Abstract translation: 夹杂在至少两个对准的导电接触件之间的各向异性导电化合物或材料的导电材料或颗粒在各向异性导电化合物固化期间机械地，磁性地或机械地和磁性地振动。 导电材料在导电材料振动之前至少部分地经受静电的，基本上均匀的直流磁场（i），（ii）之后或（iii））。

公开(公告)号：US06693243B1

公开(公告)日：2004-02-17

申请号：US09711571

申请日：2000-11-13

Applicant: Toshifumi Oida ,  Akihiro Ochii ,  Nobuyoshi Okuda ,  Yoshirou Satou ,  Katsuhiko Fujikawa

Inventor： Toshifumi Oida ,  Akihiro Ochii ,  Nobuyoshi Okuda ,  Yoshirou Satou ,  Katsuhiko Fujikawa

IPC: H05K116

CPC classification number: H05K3/341 ,  H01L23/49805 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3442 ,  H05K2201/09781 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2203/168 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: On a mounting surface of a multilayered component as a surface mounting component, an isolated electrode is arranged so as to be isolated from other terminal electrodes on the mounting surface. For solder applied to the isolated electrode, the application range can be securely limited to an area within the isolated electrode.

Abstract translation: 在作为表面安装部件的多层部件的安装面上，隔离电极配置成与安装面上的其他端子电极隔离。 对于施加到隔离电极的焊料，施加范围可以被可靠地限制在隔离电极内的区域。

公开(公告)号：US20040016505A1

公开(公告)日：2004-01-29

申请号：US10205515

申请日：2002-07-25

Applicant: Shiva Consulting, Inc.

Inventor： S. Kumar Khanna

IPC: B32B031/16

CPC classification number: H01L24/31 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29388 ,  H01L2224/29393 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/83192 ,  H01L2224/83222 ,  H01L2224/838 ,  H01L2224/83951 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K3/323 ,  H05K2201/0218 ,  H05K2201/083 ,  H05K2201/10727 ,  H05K2203/104 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: An anisotropic conductive compound is cured by exposing it to heat while in the presence of an AC magnetic field followed by a static, substantially homogeneous DC magnetic field.

Abstract translation: 各向异性导电化合物通过将其暴露于热而固化，同时在存在AC磁场，然后是静态的，基本上均匀的DC磁场的情况下。

公开(公告)号：US20030230802A1

公开(公告)日：2003-12-18

申请号：US10197986

申请日：2002-07-17

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

IPC: H01L023/48

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

公开(公告)号：US20030230801A1

公开(公告)日：2003-12-18

申请号：US10184340

申请日：2002-06-27

Inventor： Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

IPC: H01L023/34

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Abstract translation: 多芯片半导体器件（MDSCD）封装包括大体上平面的中介层，其包括具有中心插座的基板，上表面导体以及插入件下表面上的外部连接器。 导电通孔将上表面导体与外部连接器相连。 一个或多个半导体器件可以安装在插座中，以及安装在插入件上方和/或下方并附着于其上的一个或多个其它半导体器件。 封装可以被配置为具有不显着大于最大器件的占地面积和/或不显着大于所包括的器件的组合厚度的厚度。 公开了用于组装和封装来自多芯片晶片和多中介片片或条的封装的方法。 公开了将多个封装组合成单个堆叠封装的方法。 这些方法可以包括在相同封装内使用稍微侧向延伸的中间导电元件，倒装片式电连接或两者。

公开(公告)号：US06635958B2

公开(公告)日：2003-10-21

申请号：US10005703

申请日：2001-12-03

Applicant: David A. Bates ,  Stephen J. Oot ,  Robert J. Street ,  Brian L. Rowden

Inventor： David A. Bates ,  Stephen J. Oot ,  Robert J. Street ,  Brian L. Rowden

IPC: H01L2315

CPC classification number: H05K1/0243 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15313 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/10727 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A surface mount ceramic package, e.g. for a microwave or millimeter wave integrated circuit device, has outer conductive pads that are available for direct connection with traces on the printed circuit board. A metal core or base has spaces at one or more sides, e.g., voids or cutouts, where the outer pads are located. There is a first ceramic layer disposed on the core, with a central cavity for the die, and an upper or second ceramic layer. Printed traces are buried between the two layers, and vias connect the traces with the outer pads. Inner pads are located on a ledge of the first layer adjacent the cavity for connection with electrodes of the die. Each of the first and second ceramic layers may be stacked ceramic tape. The package may be LTCC or HTCC. This construction avoids inductive losses, especially at higher frequencies.

公开(公告)号：US20030111714A1

公开(公告)日：2003-06-19

申请号：US10005703

申请日：2001-12-03

Applicant: Dover Capital Formation Group

Inventor： David A. Bates ,  Stephen J. Oot ,  Robert J. Street ,  Brian L. Rowden

IPC: H01L023/02

CPC classification number: H05K1/0243 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15313 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/10727 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A surface mount ceramic package, e.g. for a microwave or millimeter wave integrated circuit device, has outer conductive pads that are available for direct connection with traces on the printed circuit board. A metal core or base has spaces at one or more sides, e.g., voids or cutouts, where the outer pads are located. There is a first ceramic layer disposed on the core, with a central cavity for the die, and an upper or second ceramic layer. Printed traces are buried between the two layers, and vias connect the traces with the outer pads. Inner pads are located on a ledge of the first layer adjacent the cavity for connection with electrodes of the die. Each of the first and second ceramic layers may be stacked ceramic tape. The package may be LTCC or HTCC. This construction avoids inductive losses, especially at higher frequencies.

Abstract translation: 表面贴装陶瓷封装，例如 对于微波或毫米波集成电路器件，具有可用于与印刷电路板上的迹线直接连接的外部导电焊盘。 金属芯或基座在一个或多个侧面具有空间，例如空隙或切口，其中外垫位于其中。 存在设置在芯上的第一陶瓷层，具有用于管芯的中心腔和上或第二陶瓷层。 印刷迹线被埋在两层之间，并且通孔将迹线与外部焊盘连接。 内部衬垫位于与腔体相邻的第一层的凸缘上，用于与模具的电极连接。 第一和第二陶瓷层中的每一个可以是层叠的陶瓷带。 包装可能是LTCC或HTCC。 这种结构避免了电感损耗，特别是在较高的频率下。

公开(公告)号：US20030025824A1

公开(公告)日：2003-02-06

申请号：US09081931

申请日：1998-05-21

Inventor： KOJI ISHIKAWA

IPC: H04N005/225

CPC classification number: H01L27/14618 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2924/3025 ,  H04N5/2253 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/303 ,  H05K3/305 ,  H05K2201/10446 ,  H05K2201/10727 ,  H05K2201/2009 ,  H05K2201/2018 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An image pickup device provided with an optical system for taking the image of an object, a photoelectric converting element for photoelectric conversion of the object image taken by the optical system, an electric signal outputting board for outputting an electrical signal from the photoelectric converting element, and a position defining member for defining the position of the optical system relative to the photoelectric converting element, wherein the electric signal outputting board is positioned between the photoelectric converting element and the position defining member.

Abstract translation: 一种图像拾取装置，具有用于拍摄物体的图像的光学系统，用于光学系统拍摄的被摄体图像的光电转换的光电转换元件，用于从光电转换元件输出电信号的电信号输出板， 以及位置限定件，用于限定光学系统相对于光电转换元件的位置，其中电信号输出板位于光电转换元件和位置限定元件之间。