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    SYSTEM AND METHOD OF TRANSFORMING A PROTEIN TO EXHIBIT QUANTUM PROPERTIES AND APPLICATIONS THEREOF
    81.
    发明申请
    SYSTEM AND METHOD OF TRANSFORMING A PROTEIN TO EXHIBIT QUANTUM PROPERTIES AND APPLICATIONS THEREOF 有权

    公开(公告)号：US20210310949A1

    公开(公告)日：2021-10-07

    申请号：US17219108

    申请日：2021-03-31

    Applicant: INDIAN INSTITUTE OF SCIENCE EDUCATION AND RESEARCH

    Inventor： Kamal Priya SINGH ,  Mehra Singh SIDHU ,  Biswajit PANDA

    IPC: G01N21/64 ,  C09K11/06 ,  C07K14/435

    Abstract: Disclosed herein is a novel phenomenon to create a nano-confined, dopant-free, electron spin-dependent fluorescence (SDF) in spider silk by fundamentally transforming its local molecular structure with femtosecond-pulses (206), having fluence below an ablation threshold. Electron-spin dependence of the fluorescent patterns created on the silk sample are confirmed by measuring the fluorescence intensity at different microwave frequencies. The fluorescent intensity exhibits microwave magnetic resonances at 2.88 GHz and 1.44 GHz at room-temperature. The SDF in laser-transformed silk can thereby enable a new-class of tough yet elastic silk-based quantum sensor and hybrid nano-mechanical ultrasensitive cantilevers on a micro-chip. X-ray diffraction (XRD), Raman-spectroscopy, direct atomistic imaging with high-resolution transmission electron microscopy (HR-TEM) and model-building studies are carried out to exhibit the change in the molecular structure and unveil creation of crown-ring like structure in nanocrystals of fluorescent silk with localized electrons possessing mid-gap states.

    A MICROFLUIDIC DEVICE WITH INTEGRATED MICRO-STRUCTURED ELECTRODES AND METHODS THEREOF
    83.
    发明申请
    A MICROFLUIDIC DEVICE WITH INTEGRATED MICRO-STRUCTURED ELECTRODES AND METHODS THEREOF 有权

    公开(公告)号：US20210162410A1

    公开(公告)日：2021-06-03

    申请号：US16954140

    申请日：2018-12-14

    Applicant: Indian Institute of Science

    Inventor： Jatin Panwar ,  Rahul Roy ,  Usama Ahmed Abbasi ,  Prakhar Jain ,  Viswanathan Kumaran

    IPC: B01L3/00 ,  G01N15/10 ,  B81B1/00 ,  B81C1/00

    Abstract: The present disclosure provides a microfluidic device comprising a set of micro-structured electrodes. The electrodes are made of a fusible alloy such as Field's Metal and are patterned on a layer of PDMS. The molten fusible alloy is poured over the patterned PDMA layer and a suction force is applied to ensure uniformity of flow of the molten metal. A second layer comprising a flow channel orthogonal to the direction of the micro-structured electrodes is disposed under the first layer to form the microfluidic device. The device shows enhanced sensitivity to RBC detection at high frequencies that are also bio-compatible (above 2 MHz). Multiple layers of the micro-structures electrodes can be sandwiched between layers of flow channels to provide a 3D microfluidic device.

    FinFET SCR with SCR implant under anode and cathode junctions
    86.
    发明授权
    FinFET SCR with SCR implant under anode and cathode junctions 有权

    公开(公告)号：US10535762B2

    公开(公告)日：2020-01-14

    申请号：US15899102

    申请日：2018-02-19

    Applicant: Indian Institute of Science

    Inventor： Mayank Shrivastava ,  Milova Paul ,  Harald Gossner

    IPC: H01L29/74 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285

    Abstract: SCRs are a must for ESD protection in low voltage—high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

    Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks
    88.
    发明授权
    Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks 有权

    公开(公告)号：US10319662B2

    公开(公告)日：2019-06-11

    申请号：US15883749

    申请日：2018-01-30

    Applicant: INDIAN INSTITUTE OF SCIENCE

    Inventor： Mayank Shrivastava ,  Milova Paul ,  Christian Russ ,  Harald Gossner

    IPC: H01L23/367 ,  H01L27/088 ,  H01L29/423 ,  H01L29/74 ,  H01L29/861 ,  H01L29/06 ,  H01L27/02 ,  H01L29/735

    Abstract: The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.

    ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)
    89.
    发明申请
    ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) 审中-公开

    公开(公告)号：US20190067440A1

    公开(公告)日：2019-02-28

    申请号：US16114650

    申请日：2018-08-28

    Applicant: INDIAN INSTITUTE OF SCIENCE

    Inventor： Mayank Shrivastava ,  Sayak Dutta Gupta ,  Ankit Soni ,  Srinivasan Raghavan ,  Navakanta Bhat

    IPC: H01L29/49 ,  H01L29/778 ,  H01L21/02

    Abstract: The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 Ωmm, interface trap density

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