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公开(公告)号：US20040097077A1
公开(公告)日：2004-05-20
申请号：US10298040
申请日：2002-11-15
Applicant: Applied Materials, Inc.
Inventor： Padmapani C. Nallan , Shu-Ting S. Hsu , Ajay Kumar
IPC: H01L021/302 , H01L021/461
CPC classification number: B81C1/00619 , B81B2203/033 , B81C2201/0112 , H01L21/30655
Abstract: A method for plasma etching a trench in a semiconductor substrate using a plurality of processing cycles comprising plasma etch and deposition periods, wherein a substrate bias power is pulsed during the etch periods.
Abstract translation: 一种用于使用包括等离子体蚀刻和沉积周期的多个处理循环来等离子体蚀刻半导体衬底中的沟槽的方法，其中衬底偏置功率在蚀刻周期期间被脉冲。
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公开(公告)号：US20030162402A1
公开(公告)日：2003-08-28
申请号：US10084622
申请日：2002-02-28
Inventor： Seung-jin Song , Kyoungdoug Min , Young-chang Joo , Hong-seok Min , Sejun Kim , Kun-joong Park
IPC: H01L021/302 , H01L021/461
CPC classification number: B81C1/00087 , B81C2201/0107 , B81C2201/0112 , B81C2201/0132 , H01L21/3081 , H01L21/32134
Abstract: A method of through-etching a substrate that is simplified and by which the flow of ions can be kept to be regular during a plasma dry etching process, is provided. According to this method, a buffer layer is formed on a first plane of the substrate, a metal layer is formed on the buffer layer, an etching mask pattern is formed on a second plane opposite to the first plane, and the substrate is through-etched with the etching mask pattern as an etching mask. Preferably, the substrate is formed of a single-crystal silicon, the buffer layer is formed of silicon dioxide, and the metal layer is formed of aluminum.
Abstract translation: 提供了一种通过蚀刻简化的衬底的方法，并且通过该方法可以在等离子体干蚀刻工艺期间将离子流保持为规则的方法。 根据该方法，在基板的第一平面上形成缓冲层，在缓冲层上形成金属层，在与第一平面相反的第二平面上形成蚀刻掩模图案， 用蚀刻掩模图案蚀刻作为蚀刻掩模。 优选地，基板由单晶硅形成，缓冲层由二氧化硅形成，金属层由铝形成。
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公开(公告)号：US11679976B2
公开(公告)日：2023-06-20
申请号：US16776098
申请日：2020-01-29
Applicant: SEIKO EPSON CORPORATION
Inventor： Shogo Inaba
IPC: G01P15/125 , B81C1/00 , B81B3/00
CPC classification number: B81C1/00515 , G01P15/125 , B81B3/0021 , B81B2201/0235 , B81B2203/0118 , B81B2203/0353 , B81B2203/04 , B81C2201/0112 , B81C2201/0132 , B81C2201/0142
Abstract: A structure forming method according to an aspect is a structure forming method for forming a first hole and a second hole having width smaller than width of the first hole in a substrate with dry etching and forming a structure. The structure forming method includes forming an etching mask on the substrate, etching a portion of the etching mask overlapping a first hole forming region where the first hole is formed, etching a portion of the etching mask overlapping a second hole forming region where the second hole is formed, and performing the dry etching of the substrate using the etching mask as a mask.
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公开(公告)号：US20180065844A1
公开(公告)日：2018-03-08
申请号：US15698597
申请日：2017-09-07
Applicant: The Government of the United States of America, as Represented by the Secretary of the Navy
Inventor： Eugene A. IMHOFF , Francis J. KUB , Karl D. HOBART , Rachael L. MYERS-WARD
IPC: B81C1/00
CPC classification number: B81C1/00619 , B81B2201/0235 , B81B2201/0242 , B81B2201/0271 , B81B2203/0109 , B81B2203/0118 , B81B2203/0127 , B81C2201/0112
Abstract: Material structures and methods for etching hexagonal, single-crystal silicon carbide (SiC) materials are provided, which include selection of on-axis or near on-axis hexagonal single-crystal SiC material as the material to be etched. The methods include etching of SiC bulk substrate material, etching of SiC material layers bonded to a silicon oxide layer, etching of suspended SiC material layers, and etching of a SiC material layer anodically bonded to a glass layer. Plasma-etched hexagonal single-crystal SiC materials of the invention may be used to form structures that include, but are not limited to, microelectromechanical beams, microelectromechanical membranes, microelectromechanical cantilevers, microelectromechanical bridges, and microelectromechanical field effect transistor devices. The material structures and methods of the invention beneficially provide improved etch symmetry, improved etch straightness, improved sidewall straightness, improved sidewall smoothness, and reduced sidewall wander compared to etched four degree off-axis SiC materials.
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公开(公告)号：US20170341931A1
公开(公告)日：2017-11-30
申请号：US15650953
申请日：2017-07-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Bucknell C. Webb
CPC classification number: B81B3/0056 , B81B2201/012 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81B2207/07 , B81C1/0015 , B81C1/00619 , B81C2201/0112 , B81C2201/0132 , B81C2201/0178 , B81C2203/0109 , B81C2203/0136 , H01H59/0009 , H01H2001/0078
Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.
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Patent Agency Ranking
公开(公告)号：US20170341930A1
公开(公告)日：2017-11-30
申请号：US15650788
申请日：2017-07-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Bucknell C. Webb
CPC classification number: B81B3/0056 , B81B2201/012 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81B2207/07 , B81C1/0015 , B81C1/00619 , B81C2201/0112 , B81C2201/0132 , B81C2201/0178 , B81C2203/0109 , B81C2203/0136 , H01H59/0009 , H01H2001/0078
Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.
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公开(公告)号：US20170320724A1
公开(公告)日：2017-11-09
申请号：US15441887
申请日：2017-02-24
Applicant: MEMS Drive, Inc.
Inventor： Roman Gutierrez , Tony Tang , Xiaolei Liu , Guiqin Wang , Matthew NG
CPC classification number: H01L21/76816 , B81B3/0045 , B81B7/0029 , B81B2203/0353 , B81C1/00674 , B81C1/00682 , B81C2201/0112 , B81C2201/0135 , H01L21/768 , H01L21/76898 , H01L23/485 , H01L2924/00 , H01L2924/00014 , H01L2924/0002 , H01L2924/1461 , H01L2924/181
Abstract: A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device, wherein the plurality of holes comprise one or more geometric shapes determined to provide specific structural characteristics desired in the MEMS device.
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公开(公告)号：US09758366B2
公开(公告)日：2017-09-12
申请号：US14969329
申请日：2015-12-15
Applicant: Bucknell C. Webb
Inventor： Bucknell C. Webb
CPC classification number: B81B3/0056 , B81B2201/012 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81B2207/07 , B81C1/0015 , B81C1/00619 , B81C2201/0112 , B81C2201/0132 , B81C2201/0178 , B81C2203/0109 , B81C2203/0136 , H01H59/0009 , H01H2001/0078
Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.
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公开(公告)号：US09738511B2
公开(公告)日：2017-08-22
申请号：US14225275
申请日：2014-03-25
Applicant: InvenSense, Inc.
Inventor： Jongwoo Shin , Kirt Reed Williams , Cerina Zhang , Kuolung (Dino) Lei
CPC classification number: B81C1/00103 , B81C2201/0112 , B81C2201/0132 , B81C2201/0133
Abstract: A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE.
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公开(公告)号：US09481563B2
公开(公告)日：2016-11-01
申请号：US14644937
申请日：2015-03-11
Applicant: Infineon Technologies AG
Inventor： Manfred Engelhardt , Martin Zgaga
CPC classification number: B81B3/001 , B81B3/0051 , B81C1/00531 , B81C1/00626 , B81C2201/0112 , B81C2201/0132 , H01L21/30655
Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.
Abstract translation: 根据半导体器件的实施例，半导体器件包括布置在微机械结构上的微机械结构和半导体材料。 半导体材料的侧表面包括第一区域和第二区域。 第一区域具有起伏，第二区域是侧表面的周边区域，朝向微机械结构减小。
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