公开(公告)号：US12041720B2

公开(公告)日：2024-07-16

申请号：US18312708

申请日：2023-05-05

Applicant: Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ren Xiong ,  Fan Li ,  Qiang Tang ,  Fei Shang ,  Haijun Qiu ,  Yuanyuan Chai ,  Huiqiang Song

IPC: H05K1/11 ,  G06F3/041 ,  G06F3/044 ,  H01R12/61 ,  H05K3/36 ,  H05K1/18 ,  H10K59/131 ,  H10K59/179

CPC classification number: H05K1/118 ,  G06F3/0412 ,  G06F3/0443 ,  G06F3/0446 ,  H01R12/61 ,  H05K3/363 ,  G06F3/04164 ,  H05K1/189 ,  H05K2201/041 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09481 ,  H05K2201/10128 ,  H10K59/131 ,  H10K59/179

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a display panel (20) and a flexible circuit board electrically connected with the display panel (20). The flexible circuit board includes a first circuit board (11), a second circuit board (22) and a conductive portion; the first circuit board (11) includes a first substrate (100), and a main contact pad, a first wire (501) and a second wire (502) provided on the first substrate (100); the second circuit board (22) includes a second substrate (200), a relay contact pad and a third wire (210) provided on the second substrate (200); and the conductive portion is configured for electrically connecting the main contact pad and the relay contact pad.

公开(公告)号：US20240234326A9

公开(公告)日：2024-07-11

申请号：US18489952

申请日：2023-10-19

Applicant: IBIDEN CO., LTD.

Inventor： Ikuya TERAUCHI ,  Shogo FUKUI ,  Ryo ANDO ,  Keisuke SHIMIZU

IPC: H01L23/538 ,  H05K1/11

CPC classification number: H01L23/5383 ,  H01L23/5386 ,  H05K1/116 ,  H05K2201/0939 ,  H05K2201/094

Abstract: A wiring substrate includes first conductor pads formed on a surface of an insulating layer, second conductor pads formed on the surface of the insulating layer, a second insulating layer covering the surface of the insulating layer and first and second conductor pads, first via conductors formed in first via holes penetrating through the second insulating layer such that the first via conductors are formed on the first conductor pads, and second via conductors formed in second via holes penetrating through the second insulating layer such that the second via conductors are formed on the second conductor pads. The first and second conductor pads are formed such that an annular width amount of each second conductor pad is smaller than an annular width amount of each first conductor pad and that a haloing amount in each second conductor pad is smaller than a haloing amount in each first conductor pad.

公开(公告)号：US20240114620A1

公开(公告)日：2024-04-04

申请号：US18238144

申请日：2023-08-25

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seung Min LEE ,  Francis SAYNES ,  Keun Woo KWON

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K1/113 ,  H05K3/3452 ,  H05K2201/0939 ,  H05K2201/094 ,  H05K2201/099

Abstract: A printed circuit board includes a first insulating layer, a plurality of first and second pads disposed on the first insulating layer, and a solder resist layer disposed on the first insulating layer, the solder resist layer having a plurality of first and second openings respectively exposing at least portions of the plurality of first and second pads. The first pad has a closed region having a side surface covered by the solder resist layer, and an open region having a side surface exposed by the first opening. The second pad has only a closed region having a side surface covered by the solder resist layer.

公开(公告)号：US20240090128A1

公开(公告)日：2024-03-14

申请号：US18261231

申请日：2021-12-03

Applicant: NITTO DENKO CORPORATION

Inventor： Yusaku TAMAKI ,  Shusaku SHIBATA ,  Teppei NIINO

IPC: H05K1/05

CPC classification number: H05K1/056 ,  H05K2201/0939 ,  H05K2201/09445

Abstract: A wiring circuit board includes a metal supporting substrate, an insulating layer, and a conductive layer in this order in a thickness direction. The conductive layer includes at least one terminal portion and a wiring portion extending from the terminal portion. The metal supporting substrate has an opening portion. The opening portion penetrates the metal supporting substrate in the thickness direction and faces the terminal portion through the insulating layer. The opening portion has a first opening peripheral edge on one side in the thickness direction and a second opening peripheral edge on the other side in the thickness direction. In a projected view in the thickness direction, the second opening peripheral edge is disposed outside the first opening peripheral edge and extends along the first opening peripheral edge.

公开(公告)号：US11924964B2

公开(公告)日：2024-03-05

申请号：US17715673

申请日：2022-04-07

Applicant: Western Digital Technologies, Inc.

Inventor： Lin Hui Chen ,  Songtao Lu ,  Chien Te Chen ,  Yu Ying Tan ,  Huang Pao Yi ,  Ching Chuan Hsieh ,  T. Sharanya Kaminda ,  Chia-Hsuan Huang

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0218 ,  H05K1/116 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

公开(公告)号：US20240049392A1

公开(公告)日：2024-02-08

申请号：US18355199

申请日：2023-07-19

Applicant: Google LLC

Inventor： John Martinis ,  Bob Benjamin Buckley ,  Xiaojun Trent Huang

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H05K3/36

CPC classification number: H05K1/144 ,  H05K1/028 ,  H05K1/115 ,  H05K1/118 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/0939 ,  H05K2201/09481

Abstract: An interconnection for flex circuit boards used, for instance, in a quantum computing system are provided. In one example, the interconnection can include a first flex circuit board having a first side and a second side opposite the first side. The interconnection can include a second flex circuit board having a third side and a fourth side opposite the third side. The first flex circuit board and the second flex circuit board are physically coupled together in an overlap joint in which a portion of the second side for the first flex circuit board overlaps a portion of the third side of the flex circuit board. The interconnection can include a signal pad structure positioned in the overlap joint that electrically couples a first via in the first flex circuit board and a second via in the second flex circuit board.

公开(公告)号：US11877728B2

公开(公告)日：2024-01-23

申请号：US17494911

申请日：2021-10-06

Applicant: CANON KABUSHIKI KAISHA

Inventor： Takahiro Furuya ,  Takatoshi Kamei ,  Tsutomu Inaba ,  Bin Qi ,  Kei Tashiro ,  Yoshihiro Egashira

IPC: A61B1/05 ,  H05K1/02 ,  H05K1/11 ,  H04N23/50 ,  A61B1/00

CPC classification number: A61B1/051 ,  H04N23/50 ,  H05K1/028 ,  H05K1/118 ,  A61B1/00105 ,  H04N23/555 ,  H05K2201/09027 ,  H05K2201/0939 ,  H05K2201/09445

Abstract: An imaging module includes an electric cable including a plurality of wirings, an imager having an imaging surface intersecting an axial direction of a distal end of the electric cable, and a flexible wiring board configured to electrically connect the imager and the electric cable. The wiring board includes a plurality of extending portions that extend from at least three portions of a connection portion connected with the imager. At least one wiring pad to which at least one of the plurality of wirings of the electric cable is connected is provided in each of the plurality of extending portions.

公开(公告)号：US20230328873A1

公开(公告)日：2023-10-12

申请号：US17715673

申请日：2022-04-07

Applicant: Western Digital Technologies, Inc.

Inventor： Lin Hui Chen ,  Songtao Lu ,  Chien Te Chen ,  Yu Ying Tan ,  Huang Pao Yi ,  Ching Chuan Hsieh ,  T. Sharanya Kaminda ,  Chia-Hsuan Huang

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0218 ,  H05K1/116 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

公开(公告)号：US11751333B2

公开(公告)日：2023-09-05

申请号：US17476625

申请日：2021-09-16

Applicant: Google LLC

Inventor： John Martinis ,  Bob Benjamin Buckley ,  Xiaojun Trent Huang

IPC: H05K1/14 ,  H05K1/11 ,  H05K1/02 ,  H05K3/36

CPC classification number: H05K1/144 ,  H05K1/028 ,  H05K1/115 ,  H05K1/118 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/0939 ,  H05K2201/09481

Abstract: An interconnection for flex circuit boards used, for instance, in a quantum computing system are provided. In one example, the interconnection can include a first flex circuit board having a first side and a second side opposite the first side. The interconnection can include a second flex circuit board having a third side and a fourth side opposite the third side. The first flex circuit board and the second flex circuit board are physically coupled together in an overlap joint in which a portion of the second side for the first flex circuit board overlaps a portion of the third side of the flex circuit board. The interconnection can include a signal pad structure positioned in the overlap joint that electrically couples a first via in the first flex circuit board and a second via in the second flex circuit board.

公开(公告)号：US11696399B2

公开(公告)日：2023-07-04

申请号：US17635916

申请日：2020-09-15

Applicant: ZTE Corporation

Inventor： Changgang Yin ,  Bi Yi ,  Zhongmin Wei

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K1/115 ,  H05K2201/0939 ,  H05K2201/09481 ,  H05K2201/09854

Abstract: A circuit board is disclosed, including a circuit board body and at least one via apparatus provided on the circuit board body. The via apparatus includes a via (101) formed on the circuit board body, a via pad (201) surrounding the via and separately provided from the via, and an electrical conductor (301) electrically connecting the via pad (201) with the via (101).