公开(公告)号：US07419382B2

公开(公告)日：2008-09-02

申请号：US11589332

申请日：2006-10-30

Applicant: Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

Inventor： Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

IPC: H01R12/00

CPC classification number: H01L24/11 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0269 ,  H05K1/112 ,  H05K1/186 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10674 ,  H05K2203/166

Abstract: According to one embodiment, a printed circuit board includes a first dielectric layer, a circuit component mounted on the first dielectric layer, and a second dielectric layer. The first dielectric layer is provided with a via hole which opens at a surface thereof and in which a conductive layer is provided, and a conductive pattern connected electrically to the conductive layer of the via hole. The circuit component is provided with a bump at least a part of which is inserted in the via hole and bonded to an inner surface of the via hole. The second dielectric layer is formed provided with another conductive pattern and laminated to the first dielectric layer to cover the circuit component.

Abstract translation: 根据一个实施例，印刷电路板包括第一电介质层，安装在第一电介质层上的电路部件和第二电介质层。 第一介电层设置有在其表面开口并且其中设置有导电层的通孔以及与通孔的导电层电连接的导电图案。 电路部件设置有凸块，其中至少一部分插入通孔中并结合到通孔的内表面。 第二电介质层被形成为设置有另一个导电图案并层压到第一电介质层以覆盖电路部件。

公开(公告)号：US20080202803A1

公开(公告)日：2008-08-28

申请号：US12007830

申请日：2008-01-16

Applicant: Kenji NAGASE ,  Kenichi KAWABATA

Inventor： Kenji NAGASE ,  Kenichi KAWABATA

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H01L24/82 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/064 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09645 ,  H05K2201/09745 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/49155 ,  H01L2924/00

Abstract: There is disclosed a wiring structure or the like capable of sufficiently improving a connection property between a body to be wired and a wiring pattern (layer) connected to the body to be wired. In a semiconductor-embedded substrate 1, conductive patterns 13 are formed on opposite surfaces of a core substrate 11, and a semiconductor device 14 is arranged in a resin layer 16 laminated on the core substrate 11. The resin layer 16 is provided with the conductive pattern 13 and bumps 14p of the semiconductor device 14, and via-holes 19a, 19b are formed through upper portions of the resin layer. In the via-holes 19a, 19b, via-hole electrode portions 23a, 23b are connected to the conductive pattern 13 and the bumps 14p of the semiconductor device 14. The via-hole electrode portions 23a, 23b are provided so that each via-hole electrode portion has a concave portion at an upper surface thereof and so that a side wall thereof including an edge portion of the concave portion does not come in contact with an inner wall of the via-hole 19a or 19b.

Abstract translation: 公开了能够充分提高被布线体与连接到待布线体的布线图案（层）之间的连接性的布线结构等。 在半导体嵌入式基板1中，在芯基板11的相对面形成有导电图案13，在层叠于芯基板11上的树脂层16内配置有半导体装置14。 树脂层16设置有导电图案13和半导体器件14的凸块14p，并且通孔21a，19b通过树脂层的上部形成。 在通孔19a，19b中，通孔电极部分23a，23b连接到导电图案13和半导体器件14的凸块14p。 通孔电极部分23a，23b设置成使得每个通孔电极部分在其上表面具有凹部，并且使得其包括凹部的边缘部分的侧壁不会接触 具有通孔19a或19b的内壁。

公开(公告)号：US20080180856A1

公开(公告)日：2008-07-31

申请号：US11701078

申请日：2007-01-31

Applicant: Toshiki Hirano ,  Haruhide Takahashi ,  Tatsumi Tsuchiya

Inventor： Toshiki Hirano ,  Haruhide Takahashi ,  Tatsumi Tsuchiya

IPC: G11B5/56

CPC classification number: G11B5/5552 ,  G11B5/4826 ,  H01L2224/11334 ,  H05K3/3442 ,  H05K3/3478 ,  H05K2201/09472 ,  H05K2203/041 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49069

Abstract: An apparatus and method for a microactuator having a bonding pad having a solder ball retainer to decrease instances of solder ball movement. The method provides a substrate for the microactuator. A conductive layer above the substrate is provided. A bonding pad having a solder ball retainer is provided and disposed above the conductive layer. The bonding pad having a solder ball retainer provides reduced instances of movement of a solder ball disposed therewithin prior to and during a reflow process performed on the solder ball.

Abstract translation: 一种微致动器的装置和方法，具有具有焊球保持器的焊盘，以减少焊球移动的实例。 该方法提供用于微致动器的衬底。 提供了衬底上方的导电层。 提供具有焊球保持器的焊盘，并设置在导电层的上方。 具有焊球保持器的焊盘提供了在焊料球之前和期间在焊球上进行的回流工艺期间设置的焊球的减少的移动实例。

公开(公告)号：US20080099539A1

公开(公告)日：2008-05-01

申请号：US11975227

申请日：2007-10-17

Applicant: Cheng Tay ,  Pek Tan ,  Swee Cheng ,  Eng Yap

Inventor： Cheng Tay ,  Pek Tan ,  Swee Cheng ,  Eng Yap

IPC: B23K31/02 ,  B23K37/00

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L21/486 ,  H05K3/3484 ,  H05K2201/0266 ,  H05K2201/035 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/043 ,  H05K2203/1476

Abstract: In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括用形成第一尺寸的焊球的焊膏填充在焊盘中形成的微孔; 以及用包括第二尺寸的焊球的焊膏涂覆所述接合焊盘，其中所述第二尺寸大于所述第一尺寸。

公开(公告)号：US20080087986A1

公开(公告)日：2008-04-17

申请号：US11986998

申请日：2007-11-27

Applicant: Ravindra Tanikella

Inventor： Ravindra Tanikella

IPC: H01L23/532 ,  H01L23/52

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

Abstract translation: 用于微电子封装的高度可靠的互连。 在一个实施例中，积聚互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如，通过催化剂的密封剂的光化学或热降解）之后，用嵌入的催化剂形成聚酰亚胺材料以促进交联。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。

公开(公告)号：US20080079140A1

公开(公告)日：2008-04-03

申请号：US11868919

申请日：2007-10-08

Applicant: Peter Salmon

Inventor： Peter Salmon

IPC: H01L23/50 ,  H05K1/16

CPC classification number: H05K3/363 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05573 ,  H01L2224/11332 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4015 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括具有窄至5微米或更小的迹线宽度的柔性多层互连电路。 与用于制造液晶显示器，LCD，面板的玻璃面板制造设备相似，优选地用于制造互连电路。 使用剥离层在玻璃面板上制造多层互连电路。 在互连电路上形成特殊的组装层，该电路包括在输入/输出（I / O）焊盘位置处形成有开口的厚电介质层。 使用刮刀将焊膏沉积在开口中以形成填充有焊料的孔。 IC芯片在I / O焊盘位置处设有金柱凸起，并且这些凸块插入孔中以形成倒装芯片连接。 IC芯片经过测试和返工。 相同的凹凸/连接可用于连接细间距电缆。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器或超级计算机实施例。

公开(公告)号：US07348215B2

公开(公告)日：2008-03-25

申请号：US10150901

申请日：2002-05-17

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L21/44

CPC classification number: H01L24/81 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/16237 ,  H01L2224/8014 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor device assembly. The flip chip-type semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having a plurality of recesses formed therein. The semiconductor die is mounted to the interposer substrate with the conductive bumps disposed in the plurality of recesses so that the die face is adjacent the facing surface of the interposer substrate. One or more openings may be provided in an opposing surface of the interposer substrate which extend to the plurality of recesses and the conductive bumps disposed therein. Dielectric filler material may then be introduced through the one or more openings to the recesses and, optionally, between the semiconductor die and interposer substrate.

Abstract translation: 一种用于将一个或多个倒装芯片配置的半导体管芯与内插器衬底组装和封装以形成倒装芯片型半导体器件组件的方法。 倒装芯片型半导体器件组件包括导电凸起的半导体管芯和在其中形成有多个凹槽的插入器衬底。 将半导体管芯安装到插入器基板上，其中导电凸块设置在多个凹部中，使得模具表面邻近插入器基板的相对表面。 可以在插入器基板的相对表面中设置一个或多个开口，该表面延伸到多个凹部和设置在其中的导电凸块。 然后可以将介质填充材料通过一个或多个开口引入到凹部中，并且可选地在半导体管芯和插入器衬底之间引入。

公开(公告)号：US20080062661A1

公开(公告)日：2008-03-13

申请号：US11649755

申请日：2007-01-05

Applicant: Byung Sung Choi ,  Hyoung Seok Kim ,  Sang Ki Hong

Inventor： Byung Sung Choi ,  Hyoung Seok Kim ,  Sang Ki Hong

IPC: H05K5/00

CPC classification number: H05K1/147 ,  G02F1/13452 ,  H05K1/0213 ,  H05K1/0215 ,  H05K3/0061 ,  H05K3/28 ,  H05K3/321 ,  H05K2201/09472 ,  H05K2201/10128 ,  H05K2201/1028

Abstract: A display assembly having a display module to receive a display signal containing prescribed information, a main circuitry supporting substrate including a ground, a flexible circuitry supporting substrate module connected to the circuitry supporting substrate to process or transfer data for prescribed information from the circuit board to the display module, the flexible circuitry supporting substrate module having recessed conductive portions, and a conductive member connected to the flexible circuitry supporting substrate module to ground the flexible circuitry supporting substrate and the display module, the conductive member including conductive tape applied to the flexible circuitry supporting substrate module and conductive paste to connect recessed conductive portions of the flexible circuitry supporting substrate module to the conductive tape. The display assembly may be formed in a mobile terminal.

Abstract translation: 一种显示器组件，具有用于接收包含规定信息的显示信号的显示模块，包括地面的主电路支撑衬底，连接到所述电路支撑衬底的柔性电路支撑衬底模块，以处理或将数据从所述电路板传送到规定信息， 所述显示模块，所述柔性电路支撑衬底模块具有凹入的导电部分，以及连接到所述柔性电路支撑衬底模块以将所述柔性电路支撑衬底和所述显示模块接地的导电构件，所述导电构件包括施加到所述柔性电路 支撑衬底模块和导电膏以将柔性电路支撑衬底模块的凹进的导电部分连接到导电带上。 显示组件可以形成在移动终端中。

公开(公告)号：US20070272436A1

公开(公告)日：2007-11-29

申请号：US11528349

申请日：2006-09-28

Applicant: Akiko Matsui

Inventor： Akiko Matsui

IPC: H05K1/16

CPC classification number: H05K1/183 ,  H05K1/116 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/10704 ,  H05K2203/0228

Abstract: A depression is formed in a first surface of a printed wiring board. A through hole penetrates through the printed wiring board from the bottom surface of the depression to a second surface of the printed wiring board. The second surface is the opposite surface of the first surface. A terminal of an electronic component is received in the through hole. The terminal has the tip end protruding from the second surface of the printed wiring board. Solder is filled in the through hole. The tip end of the terminal is allowed to protrude from the second surface of the printed wiring board even when the terminal is shorter than the original thickness of the printed wiring board. It is not necessary to change the length of the terminal.

Abstract translation: 在印刷电路板的第一表面上形成凹陷。 通孔从印刷电路板的凹陷的底面穿过印刷线路板的第二表面。 第二表面是第一表面的相对表面。 电子部件的端子被容纳在通孔中。 端子具有从印刷线路板的第二表面突出的尖端。 焊料填充在通孔中。 即使端子短于印刷电路板的原始厚度，也允许端子的顶端从印刷电路板的第二表面突出。 不需要改变终端的长度。

公开(公告)号：US07301230B2

公开(公告)日：2007-11-27

申请号：US11020226

申请日：2004-12-27

Applicant: Masateru Koide

Inventor： Masateru Koide

IPC: H01L23/12 ,  H05K1/18

CPC classification number: H01L23/50 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19106 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/381 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/09472 ,  H05K2201/10636 ,  H05K2203/0228 ,  Y02P70/611

Abstract: A laminating step includes a second step of laminating a second insulation layer on a conductive pattern last formed at a first step, roughening the surface of the laminated second insulation layer excluding a desired area, and forming a conductive layer on at least the desired area of the surface of the second insulation layer, and a processing step includes a removing step of removing an upper part of the area higher than the second insulation layer on the substrate obtained at the laminating step, and an exposing step of exposing a part of the area of a conductive pattern adjacent to the lower side of the second insulation layer.

Abstract translation: 层压步骤包括第二步骤，将第二绝缘层层压在最后形成的第一步骤的导电图案上，使层压的第二绝缘层的表面粗糙化，除去期望的区域，并且在至少所需的区域上形成导电层 第二绝缘层的表面和加工步骤包括去除在层压步骤获得的基板上高于第二绝缘层的区域的上部的去除步骤，以及暴露步骤， 的导电图案与第二绝缘层的下侧相邻。