公开(公告)号：US20100128451A1

公开(公告)日：2010-05-27

申请号：US12694951

申请日：2010-01-27

Applicant: Seiji Hayashi ,  Hideho Inagawa

Inventor： Seiji Hayashi ,  Hideho Inagawa

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0231 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/0949 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract translation: 多层印刷电路板包括：第一表面层，包括半导体集成电路;第二表面层，包括旁路电容器，并且与第一表面层相对;主电源布线层;以及第一表面层， 和第二表面层。 在多层印刷电路板中，旁路电容器的一个端子连接到从主电源布线层到半导体集成电路的电源端子的布线路径的中点，并且从第一布线路径的阻抗 到旁路电容器的端子的主电源布线层高于从旁路电容器的端子到半导体集成电路的电源端子的第二布线路径的阻抗。

公开(公告)号：US07715200B2

公开(公告)日：2010-05-11

申请号：US12232990

申请日：2008-09-26

Applicant: Jung-Chan Cho ,  Yang-Je Lee ,  Hyun-Seok Choi ,  Yong-Hyun Kim ,  Jung-Hyeon Kim ,  Hyo-Jae Bang ,  Do-Hyung Kim ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jae-Sang Baik ,  Yong-Jin Kim

Inventor： Jung-Chan Cho ,  Yang-Je Lee ,  Hyun-Seok Choi ,  Yong-Hyun Kim ,  Jung-Hyeon Kim ,  Hyo-Jae Bang ,  Do-Hyung Kim ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jae-Sang Baik ,  Yong-Jin Kim

IPC: H05K1/00

CPC classification number: H05K1/147 ,  H05K1/117 ,  H05K1/189 ,  H05K3/323 ,  H05K3/361 ,  H05K3/4691 ,  H05K2201/042 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/0949 ,  H05K2201/10159 ,  H05K2203/1572

Abstract: A stacked semiconductor module, a method of fabricating the same, and an electronic system using the module are provided. A first semiconductor module having a plurality of semiconductor devices mounted on a rigid printed circuit board (PCB) and a second semiconductor module having a plurality of other semiconductor devices mounted on a flexible PCB are provided. On the rigid PCB a number L of first tabs may be disposed on a first surface, and a number K of second tabs may be disposed on a second surface of the rigid PCB. The flexible PCB may have a number M of third tabs on a third surface, and a number N of fourth tabs on a fourth surface of the flexible PCB. The second tabs may be combined with the third tabs using a conductive adhesive. The third tabs may be electrically connected to corresponding ones of the second tabs.

Abstract translation: 提供堆叠半导体模块，其制造方法和使用该模块的电子系统。 提供了具有安装在刚性印刷电路板（PCB）上的多个半导体器件和具有安装在柔性PCB上的多个其它半导体器件的第二半导体模块的第一半导体模块。 在刚性PCB上，可以在第一表面上设置数L个第一突出部，并且可以在刚性PCB的第二表面上设置数个K个第二突片。 柔性PCB可以在第三表面上具有数量M的第三突出部，并且在柔性PCB的第四表面上可以具有数目N的第四突出部。 第二突片可以使用导电粘合剂与第三突片组合。 第三突片可以电连接到相应的第二突片。

公开(公告)号：US20100051336A1

公开(公告)日：2010-03-04

申请号：US12617191

申请日：2009-11-12

Applicant: Osamu Daikuhara ,  Toshihiro Kusagaya ,  Toru Yamakami ,  Takahiro Kondou

Inventor： Osamu Daikuhara ,  Toshihiro Kusagaya ,  Toru Yamakami ,  Takahiro Kondou

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H05K3/242 ,  H05K1/117 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/0919 ,  H05K2201/0949 ,  H05K2203/0207 ,  H05K2203/175 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board of a card edge connector type includes interconnections formed on a surface of a substrate to be electrically coupled to respective connecting terminals formed by electrolytic plating on an edge of the substrate, and connecting terminal-forming wirings being respectively in connection with the interconnections, when the connecting terminals are formed by the electrolytic plating. The interconnections are electrically isolated from the connecting terminal-forming wirings by process openings formed in the substrate.

Abstract translation: 卡边缘连接器类型的印刷电路板包括形成在基板的表面上的互连，该互连电连接到在基板的边缘上由电解电镀形成的各个连接端子，以及连接端子形成布线分别与 当连接端子由电解电镀形成时，互连。 互连通过形成在基板中的工艺开口与连接端子形成布线电隔离。

公开(公告)号：US07592703B2

公开(公告)日：2009-09-22

申请号：US11805473

申请日：2007-05-23

Applicant: Vaidyanathan Kripesh ,  Mihai Dragos Rotaru ,  Ganesh Vetrivel Periasamy ,  Seung Uk Yoon ,  Ranganathan Nagarajan

Inventor： Vaidyanathan Kripesh ,  Mihai Dragos Rotaru ,  Ganesh Vetrivel Periasamy ,  Seung Uk Yoon ,  Ranganathan Nagarajan

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L23/66 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6622 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/0949 ,  H05K2201/09809 ,  Y10T29/49117 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract translation: 实现了在制造集成电路装置中形成具有微带接地面的屏蔽通孔的新方法。 该方法包括：首先提供衬底。 蚀刻基板以形成具有微带接地层的规划屏蔽通孔的孔。 第一电介质层形成在衬底的顶侧上方并且衬套孔。 第一导电层沉积在第一介电层上并衬在孔上。 沉积第二介电层，覆盖第一导电层并衬套孔。 沉积第二导电层，覆盖第二介电层并填充孔。 第二导电层被平坦化以将第二导电层限制在孔中，从而完成具有微带接地平面的屏蔽通孔。 使用具有微带接地层的屏蔽通孔形成硅载体模块和堆叠的多个集成电路模块，以改善射频性能。

公开(公告)号：US20090227885A1

公开(公告)日：2009-09-10

申请号：US12249886

申请日：2008-10-10

Applicant: Guy Russell Lowery ,  William J. Grande

Inventor： Guy Russell Lowery ,  William J. Grande

IPC: A61M16/04 ,  A61B5/029 ,  B05D5/12

CPC classification number: A61B5/029 ,  A61B5/0421 ,  A61B5/0535 ,  A61B5/0538 ,  A61B5/6853 ,  A61B2562/0209 ,  A61B2562/046 ,  A61B2562/125 ,  H05K1/0284 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K3/4069 ,  H05K2201/0949

Abstract: The current invention provides an endotracheal tube fabricated with an array of electrodes disposed on an inflatable cuff on the tube. The array of electrodes includes multiple sense electrodes and a current electrode. The array of electrodes on the inflatable cuff is applied using a positive displacement dispensing system, such as a MicroPen®. A ground electrode is disposed on the tube approximately midway between the inflatable cuff and the midpoint of the endotracheal tube. The endotracheal tube is partially inserted into a mammalian subject's airway such that when the inflatable cuff is inflated, thereby fixing the tube in position, the array of electrodes is brought into close contact with the tracheal mucosa in relative proximity to the aorta. The endotracheal tube is useful in the measurement of cardiac parameters such as cardiac output.

Abstract translation: 本发明提供一种气管插管，其制造有设置在管上的可充气袖带上的电极阵列。 电极阵列包括多个感测电极和电流电极。 使用正位移分配系统（例如MicroPen）来施加充气袖带上的电极阵列。 接近电极位于可充气袖带和气管插管的中点之间大致中间的管上。 气管插管被部分地插入到哺乳动物受试者的气道中，使得当可膨胀的袖带被充气时，从而将管固定在适当位置，使电极阵列与气管粘膜紧密接触，相对接近主动脉。 气管内管可用于测量心脏参数，如心输出量。

公开(公告)号：US20090040741A1

公开(公告)日：2009-02-12

申请号：US12245988

申请日：2008-10-06

Applicant: Seiji Hayashi ,  Hideho Inagawa

Inventor： Seiji Hayashi ,  Hideho Inagawa

IPC: H05K1/14

CPC classification number: H05K1/0231 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/0949 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract translation: 多层印刷电路板包括：第一表面层，包括半导体集成电路;第二表面层，包括旁路电容器，并且与第一表面层相对;主电源布线层;以及第一表面层， 和第二表面层。 在多层印刷电路板中，旁路电容器的一个端子连接到从主电源布线层到半导体集成电路的电源端子的布线路径的中点，并且从第一布线路径的阻抗 到旁路电容器的端子的主电源布线层高于从旁路电容器的端子到半导体集成电路的电源端子的第二布线路径的阻抗。

公开(公告)号：US20090007425A1

公开(公告)日：2009-01-08

申请号：US12278606

申请日：2007-02-07

Applicant: Eiichi Shinada ,  Masahiro Katou ,  Noriaki Watanabe

Inventor： Eiichi Shinada ,  Masahiro Katou ,  Noriaki Watanabe

IPC: H05K3/00

CPC classification number: H05K3/4614 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/043 ,  H05K2203/061 ,  H05K2203/063 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49149

Abstract: Provided is a method for manufacturing a multilayer wiring board, by which interlayer connection is efficiently performed and a non-penetrating hole having a hollow structure or a through hole can be formed at the same time without damaging a plated portion on the inner wall of the through hole. A first printed board (1) is provided with a wiring, which has a wiring section and a bump mounting pad (14), and a substrate section. The method is provided with a step of forming a solder bump (3) on at least a bump mounting pad on the first printed board or a pad section of a second printed board (2) having the pad section (15) by using a solder paste, and a step of bonding the first printed board and the second printed board in layers by having an insulating adhesive (4) between the first printed board and the second printed board and electrically connecting the first printed board with the second printed board.

Abstract translation: 提供一种多层布线基板的制造方法，能够有效地进行层间连接，同时可以形成具有中空结构或贯通孔的非贯通孔，而不会损坏内壁上的电镀部 通孔。 第一印刷电路板（1）具有布线，布线部分和凸块安装焊盘（14）以及基板部分。 该方法具有以下步骤：在第一印刷电路板上的至少凸块安装焊盘或具有焊盘部分（15）的第二印刷电路板（2）的焊盘部分上形成焊料凸块（3） 并且通过在第一印刷电路板和第二印刷电路板之间具有绝缘粘合剂（4）并将第一印刷电路板与第二印刷电路板电连接，将第一印刷电路板和第二印刷电路板接合在一起的步骤。

公开(公告)号：US20080156521A1

公开(公告)日：2008-07-03

申请号：US11960979

申请日：2007-12-20

Applicant: Jun Karasawa ,  Syuji Hiramoto

Inventor： Jun Karasawa ,  Syuji Hiramoto

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16106 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/8121 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/82385 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0949 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: According to one embodiment, a printed wiring board includes a plurality of pads to which bumps are to be bonded respectively. The pads are each formed with a plurality of conductors, the conductors are separate from each other and correspond to one of the bumps, and the plurality of conductors define a gap therebetween, the gap being capable of receiving part of the one of the bumps.

Abstract translation: 根据一个实施例，印刷布线板包括分别焊接凸块的多个焊盘。 焊盘各自形成有多个导体，导体彼此分离并对应于凸块之一，并且多个导体在其间限定间隙，该间隙能够容纳一个凸块中的一个。

公开(公告)号：US07389929B2

公开(公告)日：2008-06-24

申请号：US11442698

申请日：2006-05-26

Applicant: William H. Havens ,  Robert J. Hennick ,  John Izzo ,  Michael D. Robinson

Inventor： William H. Havens ,  Robert J. Hennick ,  John Izzo ,  Michael D. Robinson

IPC: G06K7/10

CPC classification number: G06K7/10584 ,  G06K7/10722 ,  G06K7/10801 ,  G06K7/10861 ,  G06K7/14 ,  H05K1/18 ,  H05K3/244 ,  H05K2201/09072 ,  H05K2201/09463 ,  H05K2201/0949 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2201/10121

Abstract: An indicia decoding device can have an image sensor and a laser diode assembly configured to project laser light onto a substrate. When a trigger signal is received by the indicia decoding device, the device can calculate a delay and enable the laser diode assembly if a delay threshold is satisfied. The indicia decoding device, in one embodiment, can include a hand held housing and an imaging module carrying the image sensor.

Abstract translation: 标记解码装置可以具有被配置为将激光投射到基板上的图像传感器和激光二极管组件。 当标记解码装置接收到触发信号时，如果延迟阈值被满足，则该装置可以计算延迟并启用激光二极管组件。 在一个实施例中，标记解码装置可以包括手持外壳和承载图像传感器的成像模块。

公开(公告)号：US20080117606A1

公开(公告)日：2008-05-22

申请号：US11560382

申请日：2006-11-16

Applicant: Ulf G. Karlsson

Inventor： Ulf G. Karlsson

IPC: H05K7/00

CPC classification number: H05K1/167 ,  H01L2224/16225 ,  H01L2924/15192 ,  H05K1/115 ,  H05K1/162 ,  H05K3/4069 ,  H05K2201/0187 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/10734

Abstract: In one embodiment, a printed circuit board includes a plurality of insulating layers in which an aperture is formed through some of the layers. A resistive plug at least partially fills the aperture and contacts respective conductive members at each end of the resistive plug to form a resistive via that traverses partially through the printed circuit board. In another embodiment, a printed circuit board includes a plurality of insulating layers in which an aperture is formed through at least some of the layers. A dielectric plug at least partially fills the aperture and contacts respective conductive members at each end of the dielectric plug to form a capacitive via that traverses at least partially through the printed circuit board.

Abstract translation: 在一个实施例中，印刷电路板包括多个绝缘层，其中通过一些层形成孔。 电阻塞至少部分地填充孔并且在电阻塞的每个端部处接触相应的导电构件，以形成穿过印刷电路板的电阻通孔。 在另一个实施例中，印刷电路板包括多个绝缘层，其中通过至少一些层形成孔。 电介质塞至少部分地填充孔并且在介电塞的每个端部处接触相应的导电构件，以形成至少部分穿过印刷电路板的电容通孔。