公开(公告)号：US5244395A

公开(公告)日：1993-09-14

申请号：US921161

申请日：1992-07-29

Applicant: John A. DeSantis ,  Peter E. Albertson

Inventor： John A. DeSantis ,  Peter E. Albertson

IPC: H01R12/52 ,  H01R12/82 ,  H01R13/24 ,  H05K3/32 ,  H05K3/36

CPC classification number: H01R12/52 ,  H01R12/82 ,  H05K3/366 ,  H01R13/2414 ,  H05K2201/0314 ,  H05K2201/048 ,  H05K2201/09645 ,  H05K2201/10265 ,  H05K3/325

Abstract: A circuit interconnect system comprises a circuit pattern (22) on a rigid insulating sheet (17), forming a first circuit carrying substrate (12). A portion of the circuit pattern wraps around an edge of the insulating sheet and continues onto a vertical wall (20) of the sheet to provide a contact surface (24). An electrically conductive portion (16) of a second member (14) is mated to the first circuit carrying substrate by aligning the contact surface to the electrically conductive portion. An electrically conductive resilient material such as a conductive elastomer (35) or metal spring (35) provides electrical interconnection between the circuit pattern and the electrically conductive portion.

Abstract translation: 电路互连系统包括刚性绝缘片（17）上的电路图案（22），形成第一电路承载衬底（12）。 电路图案的一部分围绕绝缘片的边缘缠绕并且继续到片材的垂直壁（20）以提供接触表面（24）。 第二构件（14）的导电部分（16）通过将接触表面对准导电部分而与第一电路承载衬底配合。 诸如导电弹性体（35）或金属弹簧（35）的导电弹性材料提供电路图案和导电部分之间的电互连。

公开(公告)号：US3739469A

公开(公告)日：1973-06-19

申请号：US3739469D

申请日：1971-12-27

Applicant: IBM

Inventor： DOUGHERTY W

IPC: H01R12/51 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H05K3/16

CPC classification number: H05K1/0222 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2203/061 ,  Y10T29/49165

Abstract: A multilayer printed circuit board wherein via holes, which extend from one surface to the other of one layer of the board, are arranged to be concentric with through holes, which extend from the top surface of one layer to the bottom surface of another layer. The via holes are equal in size to the clearance space which would normally surround a through hole. In the manufacturing process, the large via holes are made for individual layers of the printed circuit board. During lamination, prepreg will be extruded into the via holes. After lamination, the through holes will be drilled through the center of the via holes. The prepreg which had been extruded into the via holes will insulate them from the concentric through holes.

Abstract translation: 多层印刷电路板，其中从板的一层中的一个表面延伸到另一层的通孔布置成与从一层的顶表面延伸到另一层的底表面的通孔同心。 通孔的尺寸与通常围绕通孔的间隙空间相等。 在制造过程中，为印刷电路板的各层制造大的通孔。 在层压期间，预浸料坯将被挤出到通孔中。 层压后，通孔将穿过通孔的中心。 已经挤出到通孔中的预浸料坯将使它们与同心通孔绝缘。

公开(公告)号：US2910628A

公开(公告)日：1959-10-27

申请号：US53637455

申请日：1955-09-26

Applicant: KECNER ROBERT L

Inventor： KECNER ROBERT L

IPC: H05K3/36

CPC classification number: H05K3/366 ,  H05K2201/048 ,  H05K2201/09645

公开(公告)号：US2894241A

公开(公告)日：1959-07-07

申请号：US57450756

申请日：1956-03-28

Applicant: UNITED CARR FASTENER CORP

Inventor： MCKEE WILLIAM H

IPC: H05K3/30 ,  H05K3/36

CPC classification number: H05K3/366 ,  H05K3/301 ,  H05K2201/048 ,  H05K2201/09645 ,  H05K2201/10606

公开(公告)号：US2881405A

公开(公告)日：1959-04-07

申请号：US57002556

申请日：1956-03-07

Applicant: PHILCO CORP

Inventor： YARBROUGH STANTON L

IPC: H05K3/30 ,  H05K7/12

CPC classification number: H05K7/12 ,  H05K3/306 ,  H05K2201/09072 ,  H05K2201/09645 ,  H05K2201/10424 ,  H05K2201/1059

公开(公告)号：US20230354503A1

公开(公告)日：2023-11-02

申请号：US18344652

申请日：2023-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi WU ,  Chien-Hsun LEE ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC: H05K1/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K1/0216 ,  H05K1/024 ,  H01L21/76805 ,  H05K1/0222 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/423 ,  H05K1/0245 ,  H05K3/42 ,  H05K2201/0959 ,  Y10T29/49165 ,  H05K3/4038 ,  H05K2201/0723 ,  H05K2201/09545 ,  H05K2201/09645

Abstract: An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.

公开(公告)号：US11737205B2

公开(公告)日：2023-08-22

申请号：US17884418

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi Wu ,  Chien-Hsun Lee ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H01L23/552 ,  H05K3/42 ,  H05K1/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/0216 ,  H01L21/485 ,  H01L21/486 ,  H01L21/76805 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/024 ,  H05K1/0222 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/423 ,  H05K1/0245 ,  H05K3/4038 ,  H05K3/42 ,  H05K2201/0723 ,  H05K2201/0959 ,  H05K2201/09545 ,  H05K2201/09645 ,  Y10T29/49165

Abstract: An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.

公开(公告)号：US11716811B2

公开(公告)日：2023-08-01

申请号：US17708215

申请日：2022-03-30

Applicant: IBIDEN CO., LTD.

Inventor： Kenji Murase

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K2201/09645

Abstract: A printed wiring board includes an insulating layer, and a conductor layer including a solid layer and wirings. The solid layer has an opening part. The wirings are formed in the opening part. The opening part includes first and second opening parts. The wirings include first and second wirings. The first wiring has a first land, a first portion, and a second portion. The second wiring has a second land, a third portion, and a fourth portion extending in parallel to the second portion. A first boundary between the first and second portions is in the second opening part. The first portion is bending at the first boundary and increasing distance between the first and second wirings. A second boundary between the third and fourth portions is in the second opening part. The third portion is bending at the second boundary and increasing distance between the first and second wirings.

公开(公告)号：US20190075662A1

公开(公告)日：2019-03-07

申请号：US16181180

申请日：2018-11-05

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20180175531A1

公开(公告)日：2018-06-21

申请号：US15843066

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-soo KIM

IPC: H01R12/79

CPC classification number: H01R12/79 ,  H01R12/7023 ,  H01R12/718 ,  H01R12/778 ,  H01R12/88 ,  H05K1/184 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/10356

Abstract: A connection structure between a flat cable and an electronic circuit board includes an electronic circuit board; a cable connection hole formed to penetrate the electronic circuit board; a plurality of internal contacts provided on an inner surface of the cable connection hole; and a flat cable provided with a plurality of contacts which correspond to the plurality of internal contacts of the cable connection hole and are exposed to one side surface of the flat cable. When one end of the flat cable is inserted into the cable connection hole of the electronic circuit board, the plurality of contacts of the flat cable are in contact with the plurality of internal contacts of the cable connection hole, respectively.