公开(公告)号：US20170125362A1

公开(公告)日：2017-05-04

申请号：US14928812

申请日：2015-10-30

Applicant: Infineon Technologies AG

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/498 ,  H01L25/00 ,  H01L29/16 ,  H01L23/00 ,  H01L23/495 ,  H01L25/07

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/83136 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041

Abstract: A multi-die package is manufactured by attaching a first semiconductor die made of a first semiconductor material to a thermally conductive flange via a first die attach material, and attaching a second semiconductor die to the same thermally conductive flange as the first semiconductor die via a second die attach material. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. The first semiconductor die is held in place by the first die attach material during attachment of the second semiconductor die to the flange. Leads are attached to the thermally conductive flange or to an insulating member secured to the flange. The leads provide external electrical access to the first and second semiconductor dies.

公开(公告)号：US20150340306A1

公开(公告)日：2015-11-26

申请号：US14297189

申请日：2014-06-05

Applicant: Infineon Technologies AG

Inventor： Alexander Komposch ,  Soon Ing Chew ,  Herman Hugo ,  Simon Ward

IPC: H01L23/495 ,  H03F3/213 ,  H03F1/30 ,  H03F3/195

CPC classification number: H01L23/49517 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03F1/30 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/447 ,  H03F2200/451 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/45147

Abstract: A semiconductor device package includes a solid metal base with a top surface and an electrically conductive chip mounting area on the top surface. First and second pairs of conductive leads are attached to the base and extend away from one another in opposite directions. First and second amplifiers are attached to the top surface and are electrically connected to the first and second pairs of leads. The first pair is separated from the second pair by a horizontal gap between inner edge sides of the leads. A reference line in the horizontal gap that extends perpendicular to edges of the base divides the chip mounting area into first and second chip mounting sections. An area of the first chip mounting section is smaller than an area of the second chip mounting section. The first and second leads have a smaller width than the third and fourth leads.

Abstract translation: 半导体器件封装包括具有顶表面的固体金属基底和顶表面上的导电芯片安装区域。 第一和第二对导电引线附接到基座并且在相反方向上彼此远离地延伸。 第一和第二放大器附接到顶表面并且电连接到第一和第二对引线。 第一对通过引线的内边缘之间的水平间隙与第二对分离。 垂直于基座边缘延伸的水平间隙中的参考线将芯片安装区域分成第一和第二芯片安装部分。 第一芯片安装部分的区域小于第二芯片安装部分的面积。 第一和第二引线具有比第三和第四引线更小的宽度。

公开(公告)号：US08604609B2

公开(公告)日：2013-12-10

申请号：US13654489

申请日：2012-10-18

Applicant: Infineon Technologies AG

Inventor： Anwar A. Mohammed ,  Soon Ing Chew ,  Donald Fowlkes ,  Alexander Komposch ,  Benjamin Pain-Fong Law ,  Michael Opiz Real

IPC: H01L23/34

CPC classification number: B21D22/20 ,  H01L23/04 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2924/157 ,  H01L2924/161 ,  H01L2924/171 ,  H01L2924/3511 ,  H05K3/303 ,  H05K2201/10409 ,  H05K2201/10969 ,  Y02P70/613 ,  Y10T29/4913 ,  H01L2924/014

Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.

Abstract translation: 半导体封装包括弯曲体和多个半导体管芯。 弯曲体包括第一和第二相对末端区域和中间中心区域。 弯曲体在中心区域具有第一拐点，在第一端部区域具有第二拐点，在第二端部区域具有第三拐点。 中心区域具有在第一拐点处具有最小极值的凸曲率，第一端区域具有在第二拐点处具有最大极值的凹曲率，并且第二端区域具有在第三拐点处具有最大极值的凹曲率 拐点。 多个半导体管芯在最大极值之间附接到弯曲体的上表面。

公开(公告)号：US20180254253A1

公开(公告)日：2018-09-06

申请号：US15973276

申请日：2018-05-07

Applicant: Infineon Technologies AG

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L29/16

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/83136 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041

Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

公开(公告)号：US09209116B1

公开(公告)日：2015-12-08

申请号：US14297189

申请日：2014-06-05

Applicant: Infineon Technologies AG

Inventor： Alexander Komposch ,  Soon Ing Chew ,  Herman Hugo ,  Simon Ward

IPC: H03F1/07 ,  H01L23/495 ,  H03F3/195 ,  H03F3/213 ,  H03F1/30

CPC classification number: H01L23/49517 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03F1/30 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/447 ,  H03F2200/451 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/45147

Abstract: A semiconductor device package includes a solid metal base with a top surface and an electrically conductive chip mounting area on the top surface. First and second pairs of conductive leads are attached to the base and extend away from one another in opposite directions. First and second amplifiers are attached to the top surface and are electrically connected to the first and second pairs of leads. The first pair is separated from the second pair by a horizontal gap between inner edge sides of the leads. A reference line in the horizontal gap that extends perpendicular to edges of the base divides the chip mounting area into first and second chip mounting sections. An area of the first chip mounting section is smaller than an area of the second chip mounting section. The first and second leads have a smaller width than the third and fourth leads.

Abstract translation: 半导体器件封装包括具有顶表面的固体金属基底和顶表面上的导电芯片安装区域。 第一和第二对导电引线附接到基座并且在相反方向上彼此远离地延伸。 第一和第二放大器附接到顶表面并且电连接到第一和第二对引线。 第一对通过引线的内边缘之间的水平间隙与第二对分离。 垂直于基座边缘延伸的水平间隙中的参考线将芯片安装区域分成第一和第二芯片安装部分。 第一芯片安装部分的区域小于第二芯片安装部分的面积。 第一和第二引线具有比第三和第四引线更小的宽度。

公开(公告)号：US09997476B2

公开(公告)日：2018-06-12

申请号：US14928812

申请日：2015-10-30

Applicant: Infineon Technologies AG

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/495 ,  H01L25/07 ,  H01L29/16 ,  H01L25/00

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/83136 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041

Abstract: A multi-die package is manufactured by attaching a first semiconductor die made of a first semiconductor material to a thermally conductive flange via a first die attach material, and attaching a second semiconductor die to the same thermally conductive flange as the first semiconductor die via a second die attach material. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. The first semiconductor die is held in place by the first die attach material during attachment of the second semiconductor die to the flange. Leads are attached to the thermally conductive flange or to an insulating member secured to the flange. The leads provide external electrical access to the first and second semiconductor dies.

公开(公告)号：US09293407B2

公开(公告)日：2016-03-22

申请号：US14531186

申请日：2014-11-03

Applicant: Infineon Technologies AG

Inventor： Alexander Komposch ,  Soon Ing Chew ,  Brian Condie

IPC: H01L23/34 ,  H01L21/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/047 ,  H01L23/10 ,  H01L23/13 ,  H01L21/768 ,  H01L23/48 ,  H01L23/06 ,  H01L23/14 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49844 ,  H01L21/76898 ,  H01L23/047 ,  H01L23/06 ,  H01L23/10 ,  H01L23/13 ,  H01L23/142 ,  H01L23/345 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1531 ,  H01L2924/16251 ,  H01L2924/16787 ,  H01L2924/19041 ,  H01L2924/19105 ,  Y02P80/30 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal and a second terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract translation: 半导体封装包括具有管芯附着区域和外围区域的基板，具有第一端子和背离基板的第二端子的晶体管管芯，以及框架，其包括具有附接到周边区域的第一侧面的电绝缘构件 基板的第二侧，绝缘构件的第一侧的第一金属化和绝缘构件的第二侧的第二金属化。 绝缘构件向外延伸超过基板的侧向侧壁。 第一金属化附接到第一侧的部分，其向外延伸超过基板的侧向侧壁。 第一和第二金属化物在与基板的侧向侧壁间隔开的绝缘构件的区域处电连接。

公开(公告)号：US20150048492A1

公开(公告)日：2015-02-19

申请号：US14531186

申请日：2014-11-03

Applicant: Infineon Technologies AG

Inventor： Alexander Komposch ,  Soon Ing Chew ,  Brian Condie

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/14 ,  H01L23/06

CPC classification number: H01L23/49844 ,  H01L21/76898 ,  H01L23/047 ,  H01L23/06 ,  H01L23/10 ,  H01L23/13 ,  H01L23/142 ,  H01L23/345 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1531 ,  H01L2924/16251 ,  H01L2924/16787 ,  H01L2924/19041 ,  H01L2924/19105 ,  Y02P80/30 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract translation: 半导体封装包括具有管芯附着区域和外围区域的基板，具有附接到管芯附接区域的第一端子的晶体管管芯以及背离所述基板的第二端子和第三端子，以及框架， 绝缘构件，其具有附接到所述基板的周边区域的第一侧，远离所述基板的第二侧，所述绝缘构件的所述第一侧处的第一金属化层和所述绝缘构件的第二侧的第二金属化。 绝缘构件向外延伸超过基板的侧向侧壁。 第一金属化附接到第一侧的部分，其向外延伸超过基板的侧向侧壁。 第一和第二金属化物在与基板的侧向侧壁间隔开的绝缘构件的区域处电连接。

公开(公告)号：US20130037932A1

公开(公告)日：2013-02-14

申请号：US13654489

申请日：2012-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Anwar A. Mohammed ,  Soon Ing Chew ,  Donald Fowlkes ,  Alexander Komposch ,  Benjamin Pain-Fong Law ,  Michael Opiz Real

IPC: H01L23/12 ,  F16L23/00 ,  B21D19/00 ,  H01L21/50

CPC classification number: B21D22/20 ,  H01L23/04 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2924/157 ,  H01L2924/161 ,  H01L2924/171 ,  H01L2924/3511 ,  H05K3/303 ,  H05K2201/10409 ,  H05K2201/10969 ,  Y02P70/613 ,  Y10T29/4913 ,  H01L2924/014

Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.

Abstract translation: 半导体封装包括弯曲体和多个半导体管芯。 弯曲体包括第一和第二相对末端区域和中间中心区域。 弯曲体在中心区域具有第一拐点，在第一端部区域具有第二拐点，在第二端部区域具有第三拐点。 中心区域具有在第一拐点处具有最小极值的凸曲率，第一端区域具有在第二拐点处具有最大极值的凹曲率，并且第二端区域具有在第三拐点处具有最大极值的凹曲率 拐点。 多个半导体管芯在最大极值之间附接到弯曲体的上表面。

公开(公告)号：US20160294340A1

公开(公告)日：2016-10-06

申请号：US14673928

申请日：2015-03-31

Applicant: Infineon Technologies AG

Inventor： Saurabh Goel ,  Alexander Komposch ,  Cynthia Blair ,  Cristian Gozzi

IPC: H03F3/21 ,  H01L23/498 ,  H01L25/16 ,  H03F3/19 ,  H01L25/065 ,  H01L23/66 ,  H01L25/00 ,  H03F1/02 ,  H01L23/495 ,  H01L25/07

Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces, a circuit board attached to the first main surface of the single metal flange, the circuit board having a plurality of openings which expose different regions of the first main surface of the single metal flange, and a plurality of semiconductor dies each of which is disposed in one of the openings in the circuit board and attached to the first main surface of the single metal flange. The circuit board includes a plurality of metal traces for electrically interconnecting the semiconductor dies to form a circuit. A corresponding method of manufacturing is also provided.

Abstract translation: 多空腔包装包括具有第一和第二相对主表面的单个金属凸缘，附接到单个金属凸缘的第一主表面的电路板，电路板具有多个开口，其暴露第一主表面的不同区域 的单个金属凸缘，以及多个半导体管芯，每个半导体管芯设置在电路板的一个开口中并且附接到单个金属法兰的第一主表面。 电路板包括用于电连接半导体管芯以形成电路的多个金属迹线。 还提供了相应的制造方法。