公开(公告)号：US20180212085A1

公开(公告)日：2018-07-26

申请号：US15925904

申请日：2018-03-20

Applicant: Infineon Technologies AG

Inventor： Stefan CLARA ,  Thomas Grille ,  Ursula Hedenig ,  Peter Irsigler ,  Bernhard Jakoby ,  Ventsislav M. Lavchiev ,  Thomas Ostermann ,  Thomas Popp

IPC: H01L31/0352 ,  H01L31/18 ,  H01L33/06

CPC classification number: H01L31/035254 ,  H01L31/035209 ,  H01L31/035218 ,  H01L31/173 ,  H01L31/1812 ,  H01L31/1864 ,  H01L33/06 ,  H01L2933/0033

Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 μm and 10 μm or to absorb light with a light absorption maximum at a wavelength of between 2 μm and 10 μm.

公开(公告)号：US09048244B2

公开(公告)日：2015-06-02

申请号：US14515277

申请日：2014-10-15

Applicant: Infineon Technologies AG

Inventor： Thomas Popp

IPC: H01L23/544 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3205

CPC classification number: H01L23/544 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/32051 ,  H01L29/6609 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material.

Abstract translation: 制造标记的单晶衬底的方法包括提供包含第一材料的单晶衬底，所述单晶衬底具有表面积; 在所述单晶衬底的表面积上形成标记结构，其中所述标记结构包括第一半导体材料; 以及在所述标记结构上并且至少部分地在所述单晶衬底的表面区域上沉积半导体层，其中所述半导体层包括所述第二半导体材料，并且其中所述标记结构被埋在所述第二半导体材料的下方。

公开(公告)号：US10461203B2

公开(公告)日：2019-10-29

申请号：US15925904

申请日：2018-03-20

Applicant: Infineon Technologies AG

Inventor： Stefan Clara ,  Thomas Grille ,  Ursula Hedenig ,  Peter Irsigler ,  Bernhard Jakoby ,  Ventsislav M. Lavchiev ,  Thomas Ostermann ,  Thomas Popp

IPC: H01L31/0352 ,  H01L33/06 ,  H01L31/18 ,  H01L31/173

Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 μm and 10 μm or to absorb light with a light absorption maximum at a wavelength of between 2 μm and 10 μm.

公开(公告)号：US09798132B2

公开(公告)日：2017-10-24

申请号：US14722552

申请日：2015-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Roland Meier ,  Klemens Pruegl ,  Bernhard Winkler ,  Thomas Popp ,  Raimund Foerg

IPC: G02B26/00 ,  B81C1/00

CPC classification number: G02B26/001 ,  B81C1/00158 ,  B81C1/00539 ,  G02B26/007

Abstract: Embodiments relate to microelectromechanical systems (MEMS) and more particularly to membrane structures comprising pixels for use in, e.g., display devices. In embodiments, a membrane structure comprises a monocrystalline silicon membrane above a cavity formed over a silicon substrate. The membrane structure can comprise a light interference structure that, depending upon a variable distance between the membrane and the substrate, transmits or reflects different wavelengths of light. Related devices, systems and methods are also disclosed.

公开(公告)号：US20160351739A1

公开(公告)日：2016-12-01

申请号：US15167292

申请日：2016-05-27

Applicant: Infineon Technologies AG

Inventor： Stefan CLARA ,  Thomas Grille ,  Ursula Hedenig ,  Peter Irsigler ,  Bernhard Jakoby ,  Ventsislav M. Lavchiev ,  Thomas Ostermann ,  Thomas Popp

IPC: H01L31/0352 ,  H01L31/18 ,  H01L33/06

CPC classification number: H01L31/035254 ,  H01L31/035209 ,  H01L31/035218 ,  H01L31/173 ,  H01L31/1812 ,  H01L31/1864 ,  H01L33/06 ,  H01L2933/0033

Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 μm and 10 μm or to absorb light with a light absorption maximum at a wavelength of between 2 μm and 10 μm.

Abstract translation: 半导体器件包括主要包含锗的多个量子结构。 多个量子结构形成在第一半导体层结构上。 多个量子结构的量子结构具有小于15nm的横向尺寸和每平方厘米至少8×1011个量子结构的面积密度。 多个量子结构被配置为发射波长在2μm和10μm之间的发光最大值的光，或者吸收波长在2μm和10μm之间的最大光吸收的光。

公开(公告)号：US20150037964A1

公开(公告)日：2015-02-05

申请号：US14515277

申请日：2014-10-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thomas Popp

IPC: H01L23/544 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L23/544 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/32051 ,  H01L29/6609 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material.

Abstract translation: 制造标记的单晶衬底的方法包括提供包含第一材料的单晶衬底，所述单晶衬底具有表面积; 在所述单晶衬底的表面积上形成标记结构，其中所述标记结构包括第一半导体材料; 以及在所述标记结构上并且至少部分地在所述单晶衬底的表面区域上沉积半导体层，其中所述半导体层包括所述第二半导体材料，并且其中所述标记结构被埋在所述第二半导体材料的下方。

公开(公告)号：US08901715B1

公开(公告)日：2014-12-02

申请号：US13936018

申请日：2013-07-05

Applicant: Infineon Technologies AG

Inventor： Thomas Popp

IPC: H01L29/66 ,  H01L23/544 ,  H01L29/861 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/32051 ,  H01L29/6609 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material.

Abstract translation: 制造标记的单晶衬底的方法包括提供包含第一材料的单晶衬底，所述单晶衬底具有表面积; 在所述单晶衬底的表面积上形成标记结构，其中所述标记结构包括第一半导体材料; 以及在所述标记结构上并且至少部分地在所述单晶衬底的表面区域上沉积半导体层，其中所述半导体层包括所述第二半导体材料，并且其中所述标记结构被埋在所述第二半导体材料的下方。

公开(公告)号：US11594654B2

公开(公告)日：2023-02-28

申请号：US17461159

申请日：2021-08-30

Applicant: Infineon Technologies AG

Inventor： Andre Roeth ,  Henning Feick ,  Heiko Froehlich ,  Thoralf Kautzsch ,  Olga Khvostikova ,  Stefano Parascandola ,  Thomas Popp ,  Maik Stegemann ,  Mirko Vogt

IPC: H01L31/18 ,  H01L21/02 ,  H01L31/105 ,  H01L31/028 ,  H01L31/109

Abstract: A method of generating a germanium structure includes performing an epitaxial depositing process on an assembly of a silicon substrate and an oxide layer, wherein one or more trenches in the oxide layer expose surface portions of the silicon substrate. The epitaxial depositing process includes depositing germanium onto the assembly during a first phase, performing an etch process during a second phase following the first phase in order to remove germanium from the oxide layer, and repeating the first and second phases. A germanium crystal is grown in the trench or trenches. An optical device includes a light-incidence surface formed by a raw textured surface of a germanium structure obtained by an epitaxial depositing process without processing the surface of the germanium structure after the epitaxial process.

公开(公告)号：US09508790B2

公开(公告)日：2016-11-29

申请号：US14724437

申请日：2015-05-28

Applicant: Infineon Technologies AG

Inventor： Thomas Popp ,  Stefan Pompl ,  Rudolf Berger

IPC: H01L49/02 ,  H01L27/08

CPC classification number: H01L28/90 ,  H01L27/0805

Abstract: A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.

公开(公告)号：US20150263083A1

公开(公告)日：2015-09-17

申请号：US14724437

申请日：2015-05-28

Applicant: Infineon Technologies AG

Inventor： Thomas Popp ,  Stefan Pompl ,  Rudolf Berger

IPC: H01L49/02

CPC classification number: H01L28/90 ,  H01L27/0805

Abstract: A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.

Abstract translation: 形成半导体器件的方法包括在衬底中形成具有侧壁的开口，并在开口中形成第一外延层。 第一外延层形成在侧壁的第一部分中，而不在侧壁的第二部分中生长。 在形成第一外延层之后，在开口中形成第二外延层。 第二外延层形成在侧壁的第二部分中。 在形成第二外延层之后去除第一外延层。