公开(公告)号：US09681550B2

公开(公告)日：2017-06-13

申请号：US12200749

申请日：2008-08-28

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: H05K1/18 ,  H05K1/05 ,  H05K3/28 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/92144 ,  H01L2224/96 ,  H01L2924/14 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/2018 ,  H05K2203/0156 ,  H05K2203/1469 ,  Y10T29/49124 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A frame 100 containing aperture(s) 102, 103, 104 is positioned on and joined to a permanent substrate 206a or temporary substrate 206b. Electrical component(s) 202, 203, 204 are placed into respective aperture(s) 102, 103, 104 with the leads 504, 1002 of the component(s) 202, 203, 204 positioned on and attached to the permanent substrate 206a or the temporary substrate 206b. Then an encapsulant 402, electrically insulating, but preferably thermally conductive, envelops the component(s) 102, 103, 104. At this point, temporary substrate 206b may be removed exposing component leads 1002. Or, if component(s) 102, 103, 104 are mounted on permanent substrate 206a, vias 502 extend from the surface of substrate 206a to leads 504. With leads 504, 1002 exposed, the completed subassembly 500, 1000 may be incorporated into various forms of reverse-interconnection process (RIP) assemblies as detailed in related applications.

公开(公告)号：US08246387B2

公开(公告)日：2012-08-21

申请号：US12684835

申请日：2010-01-08

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: H01R25/00

CPC classification number: H01R13/15 ,  H01R13/05 ,  Y10T29/49204

Abstract: An electronic wiping torsional connector for use in connecting to mating contacts on an insulating base. The connector includes a plurality of contacts 1-10, each having a contact area 93 adapted for wiping contact to a pad, an anchor area 92, and flattened, ribbon-like connector for receiving a wiping contact. Contacts 1-10 twist against an anchor 92 when the insulating base is inserted into the connector to provide the wiping contact.

Abstract translation: 一种用于连接到绝缘基座上的配合触点的电子擦拭扭转连接器。 连接器包括多个触点1-10，每个触点1-10具有适于擦拭与焊盘的接触的接触区域93，锚定区域92和扁平的带状连接器，用于接收擦拭触点。 当绝缘基座插入连接器以提供擦拭接触件时，接头1-10与锚固件92相扭转。

公开(公告)号：US08093712B2

公开(公告)日：2012-01-10

申请号：US13094105

申请日：2011-04-26

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: H01L21/00

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2924/19105 ,  H05K1/0278 ,  H05K3/1241 ,  H05K2201/0191 ,  H05K2201/09118 ,  H05K2203/1469

Abstract: A method (10) for manufacturing a monolithic molded electronic assembly (12). A mold (14) having first and second mold potions (14a-b) that mate to form an interior chamber (16) is provided. The mold has an injection port (22) and channel (24) connecting into the chamber. Electronic parts (30) having electronic contacts (32) are populated onto the second mold portion, to be substantially contained in the chamber. The mold potions are mated together and a liquid insulating molding material (36) is injected through the injection port channel to fill the chamber. The molding material is hardened to a solid, thereby embedding the electronic parts in the molding material as a monolithic sub-assembly (40). The monolithic sub-assembly is removed from the mold and one or more solderless conductive circuits (50) are applied to the electronic contacts of the electronic parts, thereby providing the electronic assembly.

Abstract translation: 一种用于制造单片模制电子组件（12）的方法（10）。 提供具有配合以形成内部腔室（16）的第一和第二模具部分（14a-b）的模具（14）。 模具具有连接到腔室中的注射口（22）和通道（24）。 具有电子触点（32）的电子部件（30）填充到第二模具部分上，以基本上容纳在腔室中。 将模具配合在一起，并且通过注入口通道注入液体绝缘模塑材料（36）以填充腔室。 将成型材料硬化成固体，从而将电子部件嵌入到成型材料中作为整体式子组件（40）。 将单片子组件从模具中取出，并且将一个或多个无焊导电电路（50）施加到电子部件的电子触点，从而提供电子组件。

公开(公告)号：US08026600B2

公开(公告)日：2011-09-27

申请号：US12348273

申请日：2009-01-02

Applicant: Joseph C. Fjelstad ,  Kevin P. Grundy

Inventor： Joseph C. Fjelstad ,  Kevin P. Grundy

IPC: H01L23/48

CPC classification number: H01L23/13 ,  G01R1/06772 ,  G01R31/31905 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/3011 ,  Y10T29/49222 ,  H01L2924/00

Abstract: An interconnection structure suitable for use as an IC package, probe head or other electrical termination of high density where uninterrupted controlled impedance is desired is described.

Abstract translation: 描述了适合用作需要不间断的受控阻抗的高密度的IC封装，探头或其他电终端的互连结构。

公开(公告)号：US20110127080A1

公开(公告)日：2011-06-02

申请号：US13019550

申请日：2011-02-02

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: H05K1/11 ,  H05K3/02

CPC classification number: H05K1/144 ,  H01L24/73 ,  H01L24/82 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/3025 ,  H05K1/0207 ,  H05K1/185 ,  H05K3/284 ,  H05K3/4664 ,  H05K2201/042 ,  H05K2201/043 ,  H05K2201/10189 ,  H05K2201/10318 ,  H05K2201/10386 ,  H05K2201/1056 ,  H05K2203/1316 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The present invention provides an electronic assembly 400 and a method for its manufacture 800, 900, 1000 1200, 1400, 1500, 1700. The assembly 400 uses no solder. Components 406, or component packages 402, 802, 804, 806 with I/O leads 412 are placed 800 onto a planar substrate 808. The assembly is encapsulated 900 with electrically insulating material 908 with vias 420, 1002 formed or drilled 1000 through the substrate 808 to the components' leads 412. Then the assembly is plated 1200 and the encapsulation and drilling process 1500 repeated to build up desired layers 422, 1502, 1702.

Abstract translation: 本发明提供电子组件400及其制造方法800,900,10001200,1400,1500,1700。组件400不使用焊料。 具有I / O引线412的组件406或组件封装402,802,804,806被放置在800平面衬底808上。该组件被电绝缘材料908封装，电绝缘材料908具有穿过衬底形成或钻孔1000的通孔420,1002。 808到组件引线412.然后组装电镀1200，并重复封装和钻孔工艺1500以建立所需的层422,1502,1702。

公开(公告)号：US20110065332A1

公开(公告)日：2011-03-17

申请号：US12953171

申请日：2010-11-23

Applicant: Gary Yasumura ,  William F. Wiedemann ,  Joseph C. Fjelstad ,  Para K. Segaram ,  Kevin P. Grundy

Inventor： Gary Yasumura ,  William F. Wiedemann ,  Joseph C. Fjelstad ,  Para K. Segaram ,  Kevin P. Grundy

IPC: H01R13/40 ,  H01R13/02

CPC classification number: H01R12/714 ,  H01R12/52 ,  H01R12/7082 ,  H01R13/24 ,  H01R13/6599

Abstract: An electrical connector. An electrical connector comprising a connector body having a first channel and a first conductive element extending through the first channel in a first tip section. The first tip section having a first moment arm that, when forced in contact with a first conductive surface, twists the first conductive element to produce a torsion force. The torsion force holds the first tip section in contact with the first conductive surface.

公开(公告)号：US07837477B2

公开(公告)日：2010-11-23

申请号：US12651970

申请日：2010-01-04

Applicant: Gary Yasamura ,  Joseph C. Fjelstad ,  Kevin P. Grundy ,  William F. Wiedemann ,  Matthew J. Stepovich

Inventor： Gary Yasamura ,  Joseph C. Fjelstad ,  Kevin P. Grundy ,  William F. Wiedemann ,  Matthew J. Stepovich

IPC: H01R12/00

CPC classification number: H01R13/2407 ,  H01R12/714 ,  H01R12/79 ,  H01R13/658 ,  H05K3/326 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/0979

Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.

Abstract translation: 一种电互连装置，用于在要配合的两个导电元件的端部之间建立冗余触点，产生不具有电容短截线的电互连。

公开(公告)号：US20100289130A1

公开(公告)日：2010-11-18

申请号：US12464253

申请日：2009-05-12

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: H01L23/48 ,  H05K1/11 ,  H01L21/50

CPC classification number: H05K1/181 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/14 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10537 ,  H05K2201/10689 ,  H05K2201/10924 ,  Y02P70/611 ,  H01L2924/00

Abstract: A method and apparatus for constructing a packaged integrated circuit stack 40 having at least two packaged integrated circuits 44 and 45 with an interposer 42 between the packaged integrated circuits 44 and 45. Interposer 42 is provided with apertures 47 which allow adhesive 50 to flow through interposer 42 to bond packaged integrated circuits 44 and 45 together with interposer 42. Alternate embodiments provide holes 54 to allow passage of leads 56 through interposer 42 to a substrate 60 through additional connections 48. The method describes the construction of the stack.

Abstract translation: 一种用于构建封装集成电路堆叠40的方法和装置，其具有至少两个封装的集成电路44和45以及在封装的集成电路44和45之间的插入器42.内插件42设置有孔47，允许粘合剂50流过插入件 将封装的集成电路44和45与插入器42连接在一起。替代实施例提供孔54以允许引线56通过插入件42通过附加连接48通过衬底60.该方法描述了堆叠的构造。

公开(公告)号：US20100258952A1

公开(公告)日：2010-10-14

申请号：US12755961

申请日：2010-04-07

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: H01L23/498

CPC classification number: H01L23/5387 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48137 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/181 ,  H05K3/222 ,  H05K2201/10356 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Integrated circuit chips have top and bottom surfaces. The bottom surfaces comprise a plurality of IC die terminals in flip-chip assembly with fine-pitch terminals formed on the top surface of corresponding interconnection substrate. Each IC chip includes one or more through-silicon vias and/or edge wrap connectors that extend to the top surface, terminating in IC die terminals. Flexible connectors are coupled between the IC die terminals on the top surfaces of corresponding first and second integrated circuit chips. The flexible connectors are preferably controlled impedance, and may include differential pairs, including twisted pairs, coaxial pairs, and broadside pairs. Conductive vias within the interconnection substrates couple the fine-pitch terminals to corresponding next-level terminals on the bottom surface of the respective interconnection substrates. The next level terminals of the interconnection substrates are interconnected with terminals of a printed circuit board.

Abstract translation: 集成电路芯片具有顶表面和底表面。 底表面包括倒装芯片组合中的多个IC芯片端子，其中细间距端子形成在相应互连基板的顶表面上。 每个IC芯片包括延伸到顶表面的一个或多个穿硅通孔和/或边缘包裹连接器，终止于IC芯片端子。 柔性连接器耦合在对应的第一和第二集成电路芯片的顶表面上的IC芯片端子之间。 柔性连接器优选地是受控阻抗，并且可以包括差分对，包括双绞线，同轴对和宽边对。 互连衬底内的导电孔将细间距端子耦合到相应互连衬底的底表面上的相应的下一级端子。 互连基板的下一级端子与印刷电路板的端子互连。

公开(公告)号：US20090035454A1

公开(公告)日：2009-02-05

申请号：US12182043

申请日：2008-07-29

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: B05D5/00 ,  H05K7/00

CPC classification number: H05K3/284 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K1/185 ,  H05K3/321 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2203/1316 ,  H05K2203/1469 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Electrical components 402, 504, 506 are placed on a carrier 508. Then the components are encapsulated in an electrically insulating material 404. The carrier 508 is removed and the leads 414 of the encapsulated components are registered to intermediate connectors 412 in a central bonding, or joining, material 406 and to respective leads 410 of a printed circuit board 408. The components, central bonding material, and printed circuit board are then joined and interconnected.

Abstract translation: 电气部件402,504,506被放置在载体508上。然后将部件封装在电绝缘材料404中。移除载体508，并且封装的部件的引线414以中心粘合方式与中间连接器412配准， 或者将材料406连接到印刷电路板408的各个引线410.然后将部件，中心接合材料和印刷电路板接合并互连。