公开(公告)号：US08817519B2

公开(公告)日：2014-08-26

申请号：US13672408

申请日：2012-11-08

Applicant: SK hynix Inc.

Inventor： Jeongsu Jeong ,  Youncheul Kim ,  Hyunsu Yoon ,  Yonggu Kang ,  Igsoo Kwon ,  Yeonuk Kim

IPC: G11C17/12 ,  G11C17/16 ,  G11C8/08 ,  G11C5/14

CPC classification number: G11C17/16 ,  G11C5/148 ,  G11C8/08 ,  G11C17/18

Abstract: An integrated circuit includes a high voltage generator generating a high voltage, a negative voltage generator generating a negative voltage, a divided voltage generator generating a divided voltage by dividing the power source voltage and supplying it to a read voltage terminal, a first power gate supplying the high voltage or the divided voltage to a program voltage terminal, a second power gate supplying the negative voltage or the ground voltage to a deactivation voltage terminal, a third power gate supplying the ground voltage or the divided voltage to an activation voltage terminal, and an e-fuse array circuit operating using voltage of the program voltage terminal as a program voltage, voltage of the divided voltage terminal as a read voltage, voltage of the activation voltage terminal as an activation voltage, and voltage of the deactivation voltage terminal as a deactivation voltage.

Abstract translation: 集成电路包括产生高电压的高压发生器，产生负电压的负电压发生器，分压电压发生器，通过分压电源电压产生分压，并将其提供给读电压端;第一供电电源 向编程电压端子施加高电压或分压，向停用电压端子提供负电压或接地电压的第二电源栅极，将接地电压或分压电压提供给激活电压端子的第三电源栅极，以及 使用编程电压端子的电压作为编程电压工作的电熔丝阵列电路，作为读取电压的分压电压端子的电压，作为激活电压的激活电压端子的电压，以及去激活电压端子的电压为 去激活电压。

公开(公告)号：US09165620B2

公开(公告)日：2015-10-20

申请号：US13672293

申请日：2012-11-08

Applicant: SK hynix Inc.

Inventor： Hyunsu Yoon ,  Youncheol Kim ,  Jeongsu Jeong

IPC: G11C7/00 ,  G11C7/20 ,  G11C29/44 ,  G11C29/00

CPC classification number: G11C7/20 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/802 ,  G11C2029/4402

Abstract: A memory system includes one or more memory chips, and a repair information storage chip including a nonvolatile memory configured to store a repair information of the one or more memory chips, wherein during an initial operation of the memory system, the repair information stored in the repair information storage chip is transmitted to the one or more memory chips.

Abstract translation: 存储器系统包括一个或多个存储器芯片，以及修复信息存储芯片，其包括被配置为存储一个或多个存储器芯片的修复信息的非易失性存储器，其中在存储器系统的初始操作期间，存储在存储器芯片中的修复信息 修复信息存储芯片被发送到一个或多个存储器芯片。

公开(公告)号：US09235487B2

公开(公告)日：2016-01-12

申请号：US14509820

申请日：2014-10-08

Applicant: SK hynix Inc.

Inventor： Jeongsu Jeong ,  Youncheul Kim ,  Hyunsu Yoon ,  Yonggu Kang ,  Kwidong Kim ,  Jeongtae Hwang

IPC: G11C7/00 ,  G06F11/20 ,  G11C7/20 ,  G11C29/44 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F2201/85 ,  G11C7/20 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402

Abstract: A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.

Abstract translation: 存储装置包括启动控制单元，其被配置为通过在初始化信号被激活时启动启动操作来控制启动操作的开始，并且在完成信号被激活之后忽略初始化信号，非易失性存储器单元 被配置为存储修复数据，并且在引导操作期间输出所存储的修复数据;多个寄存器，被配置为存储从非易失性存储器单元输出的修复数据;多个存储器组，被配置为用冗余代替正常单元 使用存储在多个电阻器中的相应寄存器中的修复数据的单元，以及被配置为生成完成信号以通知启动操作完成的验证单元。

公开(公告)号：US09053776B2

公开(公告)日：2015-06-09

申请号：US13672493

申请日：2012-11-08

Applicant: SK hynix Inc.

Inventor： Kwanweon Kim ,  Hyunsu Yoon ,  Jeongtae Hwang

IPC: G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C2029/4402

Abstract: A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data.

Abstract translation: 设置信息存储电路包括：第一解码器，被配置为分别响应于选择代码和第一设置信号产生第一输入使能信号，第一寄存器组分别被配置为对应于第一解码器，并且在第一输入时接收设置数据 使能分别对应于第一寄存器组的第一解码器产生的信号，并且存储所接收的设置数据，第二解码器被配置为分别响应于选择代码产生第二输入使能信号，第二组 信号和第二寄存器组，分别被配置为对应于第二解码器，并且当分别对应于第二寄存器组的第二解码器产生的第二输入使能信号被使能时接收设置数据，并存储接收的设置 数据。

公开(公告)号：US08913451B2

公开(公告)日：2014-12-16

申请号：US13672577

申请日：2012-11-08

Applicant: SK Hynix Inc.

Inventor： Hyunsu Yoon ,  Yongho Seo

IPC: G11C29/44

CPC classification number: G11C29/4401 ,  G11C29/40 ,  G11C29/44 ,  G11C2029/4002 ,  G11C2029/4402

Abstract: A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the row address to locations designated by the bank address latched in the latching in a nonvolatile memory when the data read from the multiple memory banks are different from each other.

Abstract translation: 用于测试存储器件的方法包括进入其中多个存储体以相同方式操作的测试模式，允许与多个存储体中的行地址相对应的行被激活，锁存存储体地址以及对应于 多个存储体，在由多个存储体中的列地址选择的列中写入相同的数据，读取从多个存储体写入数据中写入的数据，检查从多个存储体中的多个存储体读取的数据 数据的读取彼此相等，并且当从多个存储体读取的数据彼此不同时，将该行地址编程到由锁存在非易失性存储器中的存储体地址指定的位置。

公开(公告)号：US08885424B2

公开(公告)日：2014-11-11

申请号：US13672140

申请日：2012-11-08

Applicant: SK Hynix Inc.

Inventor： Jeongsu Jeong ,  Youncheul Kim ,  Hyunsu Yoon ,  Yonggu Kang ,  Kwidong Kim ,  Jeongtae Hwang

IPC: G11C7/10

CPC classification number: G06F11/2094 ,  G06F2201/85 ,  G11C7/20 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402

Abstract: A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.

Abstract translation: 存储装置包括启动控制单元，其被配置为通过在初始化信号被激活时启动启动操作来控制启动操作的开始，并且在完成信号被激活之后忽略初始化信号，非易失性存储器单元 被配置为存储修复数据，并且在引导操作期间输出所存储的修复数据;多个寄存器，被配置为存储从非易失性存储器单元输出的修复数据;多个存储器组，被配置为用冗余代替正常单元 使用存储在多个电阻器中的相应寄存器中的修复数据的单元，以及被配置为生成完成信号以通知启动操作完成的验证单元。

公开(公告)号：US08867288B2

公开(公告)日：2014-10-21

申请号：US13672528

申请日：2012-11-08

Applicant: SK Hynix Inc.

Inventor： Hyunsu Yoon ,  Jeongsu Jeong ,  Youncheul Kim ,  Gwangyeong Stanley Jeong ,  Hyunju Yoon

IPC: G11C29/44

CPC classification number: G11C29/4401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/4002 ,  G11C2029/4402

Abstract: A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the bank address and the row address to a nonvolatile memory when the data read from the multiple memory banks are different from each other.

Abstract translation: 用于测试存储器件的方法包括进入其中多个存储体以相同方式操作的测试模式，允许与多个存储体中的行地址相对应的行被激活，锁存存储体地址以及对应于 多个存储体，在由多个存储体中的列地址选择的列中写入相同的数据，读取从多个存储体写入数据中写入的数据，检查从多个存储体中的多个存储体读取的数据 当从多个存储体读取的数据彼此不同时，数据的读取彼此相等，并且将存储体地址和行地址编程到非易失性存储器。