公开(公告)号：US09235487B2

公开(公告)日：2016-01-12

申请号：US14509820

申请日：2014-10-08

Applicant: SK hynix Inc.

Inventor： Jeongsu Jeong ,  Youncheul Kim ,  Hyunsu Yoon ,  Yonggu Kang ,  Kwidong Kim ,  Jeongtae Hwang

IPC: G11C7/00 ,  G06F11/20 ,  G11C7/20 ,  G11C29/44 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F2201/85 ,  G11C7/20 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402

Abstract: A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.

Abstract translation: 存储装置包括启动控制单元，其被配置为通过在初始化信号被激活时启动启动操作来控制启动操作的开始，并且在完成信号被激活之后忽略初始化信号，非易失性存储器单元 被配置为存储修复数据，并且在引导操作期间输出所存储的修复数据;多个寄存器，被配置为存储从非易失性存储器单元输出的修复数据;多个存储器组，被配置为用冗余代替正常单元 使用存储在多个电阻器中的相应寄存器中的修复数据的单元，以及被配置为生成完成信号以通知启动操作完成的验证单元。

公开(公告)号：US11094369B1

公开(公告)日：2021-08-17

申请号：US16928192

申请日：2020-07-14

Applicant: SK hynix Inc.

Inventor： Nogeun Joo ,  Jungho Lim ,  Byeongchan Choi ,  Jeongtae Hwang

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10

Abstract: A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits, each of the plurality of address storing circuits suitable for storing a sampling address as a latch address, a valid bit indicating whether the latch address is valid, and a valid-lock bit indicating whether the latch address is accessed more than a certain number of times, each of the plurality of address storing circuits further suitable for outputting the latch address as a target address according to the valid bit and valid-lock bit; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to a refresh command.

公开(公告)号：US09053776B2

公开(公告)日：2015-06-09

申请号：US13672493

申请日：2012-11-08

Applicant: SK hynix Inc.

Inventor： Kwanweon Kim ,  Hyunsu Yoon ,  Jeongtae Hwang

IPC: G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C2029/4402

Abstract: A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data.

Abstract translation: 设置信息存储电路包括：第一解码器，被配置为分别响应于选择代码和第一设置信号产生第一输入使能信号，第一寄存器组分别被配置为对应于第一解码器，并且在第一输入时接收设置数据 使能分别对应于第一寄存器组的第一解码器产生的信号，并且存储所接收的设置数据，第二解码器被配置为分别响应于选择代码产生第二输入使能信号，第二组 信号和第二寄存器组，分别被配置为对应于第二解码器，并且当分别对应于第二寄存器组的第二解码器产生的第二输入使能信号被使能时接收设置数据，并存储接收的设置 数据。

公开(公告)号：US08885424B2

公开(公告)日：2014-11-11

申请号：US13672140

申请日：2012-11-08

Applicant: SK Hynix Inc.

Inventor： Jeongsu Jeong ,  Youncheul Kim ,  Hyunsu Yoon ,  Yonggu Kang ,  Kwidong Kim ,  Jeongtae Hwang

IPC: G11C7/10

CPC classification number: G06F11/2094 ,  G06F2201/85 ,  G11C7/20 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402

Abstract: A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.

Abstract translation: 存储装置包括启动控制单元，其被配置为通过在初始化信号被激活时启动启动操作来控制启动操作的开始，并且在完成信号被激活之后忽略初始化信号，非易失性存储器单元 被配置为存储修复数据，并且在引导操作期间输出所存储的修复数据;多个寄存器，被配置为存储从非易失性存储器单元输出的修复数据;多个存储器组，被配置为用冗余代替正常单元 使用存储在多个电阻器中的相应寄存器中的修复数据的单元，以及被配置为生成完成信号以通知启动操作完成的验证单元。