公开(公告)号：US11843041B2

公开(公告)日：2023-12-12

申请号：US17856892

申请日：2022-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Jung-Hao Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84 ,  H01L29/165

CPC classification number: H01L29/517 ,  H01J37/00 ,  H01L21/0228 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/7848

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

公开(公告)号：US20190252217A1

公开(公告)日：2019-08-15

申请号：US16394089

申请日：2019-04-25

Applicant: Tokyo Electron Limited

Inventor： Masahiro Tabata ,  Sho Kumakura

IPC: H01L21/67 ,  H01J37/00 ,  H01L21/311

CPC classification number: H01L21/67069 ,  H01J37/00 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/67

Abstract: Generation of a deposit can be suppressed and high selectivity can be acquired when etching a first region made of silicon nitride selectively against a second region made of silicon oxide. A method includes preparing a processing target object having the first region and the second region within a chamber provided in a chamber main body of a plasma processing apparatus; generating plasma of a first gas including a gas containing hydrogen within the chamber to form a modified region by modifying a part of the first region with active species of the hydrogen; and generating plasma of a second gas including a gas containing fluorine within the chamber to remove the modified region with active species of the fluorine.

公开(公告)号：US20190109000A1

公开(公告)日：2019-04-11

申请号：US15729853

申请日：2017-10-11

Applicant: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC

Inventor： Aiden Alexander Martin

IPC: H01L21/02 ,  H01L21/67 ,  C23C14/22 ,  C23C14/06

CPC classification number: H01L21/02529 ,  C23C14/0635 ,  C23C14/221 ,  H01J37/00 ,  H01L21/67103 ,  H01L21/67213 ,  H01L21/67253

Abstract: A method for produce a silicon-carbide film by admitting a gaseous silicon-carbide precursor into a vacuum chamber containing a substrate and directing an electron beam into the vacuum chamber onto to the surface of the substrate. The electron beam dissociates the gaseous silicon-carbide precursor at the surface of the substrate creating non-volatile fragments that bind to the substrate surface forming a silicon-carbide film.

公开(公告)号：US20180243789A1

公开(公告)日：2018-08-30

申请号：US15750815

申请日：2017-03-31

Applicant: LG CHEM, LTD.

Inventor： Hee Wang YANG ,  Jang Yeon HWANG ,  Seong Hwan LEE

IPC: B05D3/14 ,  C08J7/04 ,  B05D7/04 ,  B05D7/26 ,  B05D7/00

CPC classification number: B05D3/148 ,  B05D7/04 ,  B05D7/26 ,  B05D7/54 ,  B32B7/02 ,  B32B27/08 ,  B32B27/18 ,  B32B27/28 ,  B32B38/0008 ,  B32B2457/12 ,  B32B2457/20 ,  C08J7/042 ,  C08J7/123 ,  C08J2367/02 ,  C08J2433/04 ,  C08J2435/02 ,  C08J2483/16 ,  H01J37/00

Abstract: The present application relates to a method for preparing a barrier film. The present application can provide a method for preparing a barrier film having excellent barrier characteristics and optical performances. The barrier film produced by the method of the present application can be effectively used not only for packaging materials of as foods or medicines, and the like, but also for various applications, such as members for FPDs (flat panel displays) such as LCDs (Liquid Crystal Displays) or solar cells, substrates for electronic papers or OLEDs (Organic Light Emitting Diodes), or sealing films.

公开(公告)号：US20180193814A1

公开(公告)日：2018-07-12

申请号：US15905426

申请日：2018-02-26

Applicant: Chow Tai Fook Jewellery Company Limited

Inventor： Koon Chung HUI ,  Ho CHING ,  Ching Tom KONG

IPC: B01J19/08 ,  C30B33/04 ,  C30B29/04 ,  H01J37/00 ,  B41M3/14 ,  C30B29/16 ,  C30B29/34 ,  C30B29/20

CPC classification number: B01J19/081 ,  B41M3/14 ,  C30B29/04 ,  C30B29/16 ,  C30B29/20 ,  C30B29/34 ,  C30B33/04 ,  H01J37/00 ,  H01J37/317 ,  H01J2237/31713 ,  H01J2237/31737 ,  Y10T428/24355

Abstract: A method of forming one or more protrusions on an outer surface of a polished face of a solid state material, said method including the step of applying focused inert gas ion beam local irradiation towards an outer surface of a polished facet of a solid state material in a way of protruding top surface material; wherein irradiated focused inert gas ions from said focused inert gas ion bean penetrate the outer surface of said polished facet of said solid state material; and wherein irradiated focused inert gas ions cause expansive strain within the solid state crystal lattice of the solid state material below said outer surface at a pressure so as to induce expansion of solid state crystal lattice, and form a protrusion on the outer surface of the polished face of said solid state material.

公开(公告)号：US20180158713A1

公开(公告)日：2018-06-07

申请号：US15822568

申请日：2017-11-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI ,  NORIYUKI MATSUBARA ,  AKIHIRO ITOU

IPC: H01L21/683 ,  H01L21/311 ,  H01L21/78 ,  H01L21/304 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01J37/00 ,  H01L21/304 ,  H01L21/31138 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/78 ,  H01L24/13 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/95001

Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.

公开(公告)号：US20180023193A1

公开(公告)日：2018-01-25

申请号：US15654436

申请日：2017-07-19

Applicant: Applied Materials, Inc.

Inventor： Sanjeev BALUJA ,  Kalyanjit GHOSH ,  Ren-Guan DUAN ,  Mayur G. KULKARNI ,  Gregory SIU ,  Praket P. JHA ,  Deenesh PADHI ,  Lei GUO ,  Wei Min CHAN ,  Ajit BALAKRISHNA

IPC: C23C16/44

CPC classification number: C23C16/4405 ,  C23C16/4408 ,  C23C16/45519 ,  H01J37/00

Abstract: Embodiments disclosed herein generally relate to systems and methods to prevent free radical damage to sensitive components in a process chamber and optimizing flow profiles. The processing chamber utilizes a cover substrate on lift pins and an inert bottom purge flow to shield the substrate support from halogen reactants. During a clean process, the cover substrate and the purge flow restricts halogen reactants from contacting the substrate support. The method of cleaning includes placing a cover substrate on a plurality of lift pins that extend through a substrate support in a processing chamber, raising the cover substrate via the lift pins to expose a space between the cover substrate and the substrate support, supplying a halogen containing gas into the processing chamber, supplying a second gas through an opening in the processing chamber, and flowing the second gas through the space between the cover substrate and the substrate support.

公开(公告)号：US20170315455A1

公开(公告)日：2017-11-02

申请号：US15143246

申请日：2016-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jensen Yang ,  Shy-Jay Lin ,  Yen-Hao Huang

IPC: G03F7/20

CPC classification number: H01J37/00 ,  H01J37/3174 ,  H01J2237/31762

Abstract: A system includes a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable; a switching device that is coupled to the DPG, the switching device configured to route a packet to the DPG so as to control at least one of the pixels, the switching device further comprising: a plurality of input buffers configured to receive and store the packet through a transmission line; a plurality of output buffers; a plurality of memory devices, wherein each of the plurality of memory devices is associated with one of the plurality of output buffers; and a scheduling engine that is coupled to the plurality of input buffers, the plurality of output buffers, and the plurality of memory devices and is configured to determine a routing path for the packet stored in one of the input buffers based on an availability of the output buffers and a vacancy level the memory devices.

公开(公告)号：US20170283950A1

公开(公告)日：2017-10-05

申请号：US15444434

申请日：2017-02-28

Applicant: HITACHI KOKUSAI ELECTRIC INC.

Inventor： Tsuyoshi TAKEDA

IPC: C23C16/50 ,  C23C16/455 ,  C23C16/40 ,  H01L21/02

CPC classification number: C23C16/50 ,  C23C16/401 ,  C23C16/402 ,  C23C16/4412 ,  C23C16/452 ,  C23C16/455 ,  C23C16/45578 ,  H01J37/00 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228

Abstract: In a process chamber in which a substrate is processed, a gas supply unit is in the process chamber and configured to supply a process gas that processes the substrate. A plasma generation unit is in the process chamber and configured to activate the process gas, and a buffer part is configured to form a buffer chamber accommodating at least a part of the plasma generation unit and include a gas supply hole through which the activated process gas is supplied to the substrate. The buffer part includes a groove portion in which a part of the gas supply hole is cut out.

公开(公告)号：US09694115B2

公开(公告)日：2017-07-04

申请号：US14894088

申请日：2014-05-28

Applicant: Lifetech Scientific (Shenzhen) Co., Ltd.

Inventor： Deyuan Zhang ,  Wenbin Wang ,  Ziqiang Liu

IPC: C23F1/00 ,  A61L31/02 ,  A61L31/14 ,  A61L31/16 ,  C23C8/02 ,  C23C8/26 ,  C23C8/38 ,  C23C8/80 ,  H01J37/00

CPC classification number: A61L31/022 ,  A61L31/148 ,  A61L31/16 ,  C23C8/02 ,  C23C8/26 ,  C23C8/38 ,  C23C8/80 ,  C23F1/00 ,  H01J37/00 ,  H01J2237/316

Abstract: Disclosed is a manufacturing method of an iron-based alloy medical apparatus, comprising: nitriding the iron-based alloy preformed unit at 350-550° C. for 30-100 minutes; and ion etching the iron-based alloy preformed unit with an ion etching time of 80-110% of the nitriding time. Ion nitriding and ion etching can be performed in situ in the same equipment using this manufacture method with high production efficiency, and in the ion nitriding and ion etching process, nitrogen atoms continuously permeate the preformed unit, making the time it takes for the medical apparatus to be absorbed by the human body and both the hardness and strength of the instrument surface achieve requirements.