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公开(公告)号：KR102061306B1
公开(公告)日：2019-12-31
申请号：KR1020130068263
申请日：2013-06-14
Applicant: 한국전자통신연구원
IPC: H01L29/786 , H01L21/336
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公开(公告)号：KR101775563B1
公开(公告)日：2017-09-07
申请号：KR1020110085561
申请日：2011-08-26
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
IPC: H03K19/094 , H03K19/20
Abstract: 본발명은인버터, NAND 게이트및 NOR 게이트에관한것으로서, 게이트에인가되는전압에따라제1 전원전압을출력단자로출력하는제2 박막트랜지스터로이루어지는풀업부; 게이트에인가되는입력신호에따라그라운드전압을출력단자로출력하는제5 박막트랜지스터로이루어지는풀다운부; 및상기입력신호에따라제2 전원전압또는상기그라운드전압을상기제2 박막트랜지스터의게이트에인가하는풀업구동부를포함한다.
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公开(公告)号：KR1020150131455A
公开(公告)日：2015-11-25
申请号：KR1020140057900
申请日：2014-05-14
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
IPC: G09G3/20
Abstract: 게이트구동회로는, 임의의세 개의연속된스테이지들을포함하는복수의스테이지들중, 제1 스테이지의타이밍신호입력단자와제3 스테이지의타이밍신호출력단자가연결되며, 제2 스테이지의캐리단자와제3 스테이지의입력단자가연결된게이트구동회로에있어서, 제2 스테이지는제1 스테이지로부터캐리신호를수신하는입력부, 캐리신호의레벨에따라제1 전압레벨의클럭신호를제1 노드에인가하며, 제2 노드의전압을제1 전압레벨보다상승시키는부트스트래핑부, 제1 노드와 제1 접지단자에연결되며, 제1 노드의전압레벨에따라출력단자의출력신호를제1 접지전압으로풀-다운시키는제1 풀-다운부, 및제1 노드와연결되며, 캐리단자및 타이밍신호출력단자의출력신호를제1 혹은제2 접지전압으로풀-다운시키는제2 풀-다운부를포함하되, 제2 풀-다운부는타이밍신호출력단자에다이오드-커넥션으로연결된제1 트랜지스터및 캐리단자와제1 접지단자에연결된제2 트랜지스터를포함하고, 제1 노드가제2 전압레벨일 때, 제2 트랜지스터가턴-오프상태이면, 캐리단자및 타이밍신호출력단자는제2 접지전압으로풀-다운되고, 제2 트랜지스터가턴-온상태이면, 타이밍신호출력단자는제1 접지전압으로풀-다운되고, 제3 스테이지의제2 노드로부터캐리단자에인가되는방전전압을제1 접지단자로인가하며, 제1 트랜지스터는방전전압이출력단자에인가되지않도록한다. 따라서, 게이트구동회로는출력신호에서리플(Ripple) 현상을감소시킴으로써, 출력신호의효율을향상시킬수 있다. 또한본 발명의실시예에따르면, 이전스테이지에서출력된캐리신호가다음스테이지의입력단자에효과적으로전달될수 있다.
Abstract translation: 门驱动电路技术领域本发明涉及栅极驱动电路。 第一级的定时信号输入端连接到第三级的定时信号输出端。 第二级的进位端连接到第三级的输入端。 第二级包括：输入单元，其从第一级接收进位信号;自举单元，其根据进位信号的电平将第一电压电平的时钟信号施加到第一节点;第一下拉单元 其连接到第一节点和第一接地终端，以及第二下拉单元，其连接到第一节点。 根据本发明的实施例的栅极驱动电路通过减少输出信号中的纹波现象来提高输出信号的效率。
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公开(公告)号：KR1020140021096A
公开(公告)日：2014-02-20
申请号：KR1020120086234
申请日：2012-08-07
Applicant: 한국전자통신연구원
IPC: H01L29/786 , H01L21/336
CPC classification number: H01L29/66742 , H01L29/66969 , H01L29/78618 , H01L29/7869 , H01L29/45
Abstract: The present invention relates to a self-aligned thin film transistor with a doping barrier for controlling the diffusion level of a doping barrier using the doping barrier in a thin film transistor having a self-alignment structure and a manufacturing method thereof. A self-aligned thin film transistor with a doping barrier includes an active layer formed on a substrate and having a first doping region, a second doping region and a channel region, a gate insulating layer formed on the channel region, a gate electrode formed on the gate insulating layer, a doping source layer formed on the first and the second doping region, a doping barrier formed between the doping source and the first and the second doping region.
Abstract translation: 本发明涉及具有掺杂势垒的自对准薄膜晶体管，该掺杂势垒用于在具有自对准结构的薄膜晶体管及其制造方法中使用掺杂势垒来控制掺杂势垒的扩散级。 具有掺杂势垒的自对准薄膜晶体管包括形成在衬底上并具有第一掺杂区，第二掺杂区和沟道区的有源层，形成在沟道区上的栅极绝缘层，形成在栅极上的栅电极 栅极绝缘层，形成在第一和第二掺杂区域上的掺杂源层，形成在掺杂源与第一和第二掺杂区之间的掺杂势垒。
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Patent Agency Ranking
公开(公告)号：KR1020130113972A
公开(公告)日：2013-10-16
申请号：KR1020130017100
申请日：2013-02-18
Applicant: 한국전자통신연구원
IPC: H01L29/786 , H01L21/336 , G02F1/136 , H01L51/50
CPC classification number: H01L29/66742 , H01L27/3258 , H01L29/41733 , H01L29/78606 , H01L29/78648 , H01L29/7869
Abstract: PURPOSE: A method for manufacturing an oxide thin film transistor is provided to improve barrier characteristics by including an etch stop layer. CONSTITUTION: A gate electrode is formed on a substrate. A gate insulating layer is formed on the front surface of the substrate. An oxide semiconductor layer (140) is formed on the gate insulating layer. A first etch stop layer (150) is formed on the oxide semiconductor layer. A second etch stop layer (160) is formed on the first etch stop layer.
Abstract translation: 目的：提供一种用于制造氧化物薄膜晶体管的方法，以通过包括蚀刻停止层来改善阻挡特性。 构成：在基板上形成栅电极。 栅极绝缘层形成在基板的前表面上。 在栅极绝缘层上形成氧化物半导体层（140）。 在氧化物半导体层上形成第一蚀刻停止层（150）。 在第一蚀刻停止层上形成第二蚀刻停止层（160）。
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公开(公告)号：KR1020120079796A
公开(公告)日：2012-07-13
申请号：KR1020110068813
申请日：2011-07-12
Applicant: 한국전자통신연구원
CPC classification number: H01L51/5284 , H01L27/322 , H01L27/3244 , H01L51/5036
Abstract: PURPOSE: An active matrix organic light emitting display and a manufacturing method thereof are provided to preventing the degradation of a contrast ratio by forming a black matrix on a partial region of a substrate before a thin film transistor is formed. CONSTITUTION: A thin film transistor(130) is formed on the top of a black matrix. A protective film(140) covers a front side of the thin film transistor. A flat layer(150) is formed on the top of the protective film. A color filter(160) is formed on an upper portion of an opposite side flat layer on which the thin film transistor is formed. An organic electro luminescence device(180) is formed on the top of the color filter.
Abstract translation: 目的：提供一种有源矩阵有机发光显示器及其制造方法，用于通过在形成薄膜晶体管之前在衬底的部分区域上形成黑色矩阵来防止对比度的降低。 构成：在黑矩阵的顶部形成薄膜晶体管（130）。 保护膜（140）覆盖薄膜晶体管的前侧。 在保护膜的顶部形成平坦层（150）。 在形成有薄膜晶体管的相对侧平坦层的上部形成滤色器（160）。 有机电致发光器件（180）形成在滤色器的顶部。
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公开(公告)号：KR1020110134145A
公开(公告)日：2011-12-14
申请号：KR1020100053968
申请日：2010-06-08
Applicant: 한국전자통신연구원
CPC classification number: G11C11/22
Abstract: PURPOSE: A memory cell and a memory device using the same are provided to improve integrity of the memory cell by reducing the number of wires for one memory cell. CONSTITUTION: A reference voltage is applied to a drain of a ferroelectric transistor. A first switch connects a source of the ferroelectric transistor to a first line(L1) in response to a scan signal. A second switch(TB) connects a gate of the ferroelectric transistor to a second line(L2) in response to the scan signal. The scan line is connected to the gate of the first switch and the second switch and applies the scan signal. A reference line is connected to the drain of the ferroelectric transistor.
Abstract translation: 目的：提供一种存储单元和使用该存储单元的存储器件，以通过减少一个存储器单元的导线数来改善存储单元的完整性。 构成：将参考电压施加到铁电晶体管的漏极。 第一开关响应于扫描信号将铁电晶体管的源极连接到第一线（L1）。 第二开关（TB）响应于扫描信号将铁电晶体管的栅极连接到第二线（L2）。 扫描线连接到第一开关和第二开关的栅极并施加扫描信号。 参考线连接到铁电晶体管的漏极。
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公开(公告)号：KR1020110113273A
公开(公告)日：2011-10-17
申请号：KR1020100032559
申请日：2010-04-09
Applicant: 한국전자통신연구원
Abstract: 본 발명은 전력 절감형 액자 겸용 텔레비전에 관한 것으로, 본 발명에 따른 전력 절감형 액자 겸용 텔레비전은 제1영상을 표시하는 제1디스플레이; 제2영상을 표시하는 저전력형 제2디스플레이; 및 상기 제1디스플레이를 통해 상기 제1영상을 표시하지 않는 경우 상기 제2디스플레이를 통해 상기 제2영상을 표시하도록 제어하는 디스플레이 제어부를 포함한다.
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公开(公告)号：KR1020090105781A
公开(公告)日：2009-10-07
申请号：KR1020080081810
申请日：2008-08-21
Applicant: 한국전자통신연구원
IPC: H01L21/3063
CPC classification number: H01L21/32134 , C09K13/04 , C23F1/16
Abstract: PURPOSE: The composition for etching a multilayer conductive thin film and an etching method using the same are provided to improve yield by forming a minute pattern with the wet etching. CONSTITUTION: The composition of the multilayer conductive thin film includes the acid for etching and the water. The acid for etching is selected from the group of hydrogen, nitrogen, hydrochloric acid, and sulfuric acid. The acid forms the complex with an oxide layer(20,40) and a metal layer(30). The transparent conductive film includes the water.
Abstract translation: 目的：提供用于蚀刻多层导电薄膜的组合物和使用其的蚀刻方法，以通过用湿蚀刻形成微小图案来提高产率。 构成：多层导电薄膜的组成包括蚀刻用酸和水。 用于蚀刻的酸选自氢，氮，盐酸和硫酸。 酸与氧化物层（20,40）和金属层（30）形成络合物。 透明导电膜包括水。
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