公开(公告)号：US20140120715A1

公开(公告)日：2014-05-01

申请号：US14147891

申请日：2014-01-06

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Kung-An Lin ,  Sheng-Hui Chen

IPC: H01L21/768

CPC classification number: H01L21/76885 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16058 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers.

Abstract translation: 半导体制造方法包括提供具有金属层的载体，其中所述金属层包括多个基底区域和多个外部横向区域; 形成第一光致抗蚀剂层; 形成多个轴承部; 移除第一光致抗蚀剂层以露出轴承部分，每个轴承部分包括具有第一区域和第二区域的支承表面; 形成用于露出所述支承表面的第一区域的第二光致抗蚀剂层; 形成多个连接部，其中，所述支承面的所述第一区域被所述连接部覆盖，以使每个连接部分与每个支承部分连接以形成卡扣凸块; 去除金属层的外侧面区域，以使基部区域形成多个凸起下的冶金层。

公开(公告)号：US20240194646A1

公开(公告)日：2024-06-13

申请号：US18374725

申请日：2023-09-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chen-Yu Wang ,  Chih-Hao Chiang ,  Pai-Sheng Cheng ,  Kung-An Lin ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Wen-Cheng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/13541 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

公开(公告)号：US20230378044A1

公开(公告)日：2023-11-23

申请号：US18109337

申请日：2023-02-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Chih-Hao Chiang ,  Chen-Yu Wang ,  Kung-An Lin ,  Pai-Sheng Cheng

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13014 ,  H01L2224/16227

Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

公开(公告)号：US09159660B2

公开(公告)日：2015-10-13

申请号：US14042979

申请日：2013-10-01

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Lung-Hua Ho ,  Chaun-Yu Wu ,  Kung-An Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

Abstract translation: 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。

公开(公告)号：US20140117540A1

公开(公告)日：2014-05-01

申请号：US14148038

申请日：2014-01-06

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Kung-An Lin ,  Sheng-Hui Chen

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers.

公开(公告)号：US20140027905A1

公开(公告)日：2014-01-30

申请号：US14042979

申请日：2013-10-01

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Lung-Hua Ho ,  Chaun-Yu Wu ,  Kung-An Lin

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

Abstract translation: 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。

公开(公告)号：US20230420287A1

公开(公告)日：2023-12-28

申请号：US18137799

申请日：2023-04-21

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Ching-Wen Chen ,  Chen-Lung Teng ,  Kung-An Lin ,  Chen-Yu Wang

IPC: H01L21/687 ,  H01L21/67

CPC classification number: H01L21/68721 ,  H01L21/67092 ,  H01L21/68735

Abstract: A clamp assembly includes at least one clamp which is provided to clamp a workpiece in electroless plating, etching, electroplating or cleaning process. The clamp includes a base, a clamping element and a limiting element. The base is mounted on a carrier and includes a guide hole and a first limiting hole which are communicated with each other. The clamping element includes a guide rod and a second limiting hole, the guide rod is inserted into the guide hole to allow the second limiting hole located on the guide hole to be communicated with the first limiting hole. The limiting element is inserted into the first and second limiting holes to integrate the base with the clamping element for clamping the workpiece.

公开(公告)号：US20140097540A1

公开(公告)日：2014-04-10

申请号：US13677518

申请日：2012-11-15

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Hsiang-Chin Chiu ,  Sheng-Ming Wu ,  Kuang-Hao Yang ,  Kung-An Lin ,  Chen-Yu Wang

IPC: H01L23/373 ,  H01L23/482

CPC classification number: H01L23/3735 ,  H01L21/6836 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/4827 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2924/10253

Abstract: A semiconductor structure includes a silicon substrate, a titanium layer, a nickel layer, a silver layer and a metallic adhesion layer, wherein the silicon substrate comprises a back surface, and the titanium layer comprises an upper surface. The titanium layer is formed on the back surface, the nickel layer is formed on the upper surface, the silver layer is formed on the nickel layer, and the metallic adhesion layer is formed between the nickel layer and the silver layer.

Abstract translation: 半导体结构包括硅衬底，钛层，镍层，银层和金属粘合层，其中硅衬底包括背面，并且钛层包括上表面。 钛层形成在背面，镍层形成在上表面，银层形成在镍层上，并且金属粘合层形成在镍层和银层之间。