公开(公告)号：WO2006117394A2

公开(公告)日：2006-11-09

申请号：PCT/EP2006062046

申请日：2006-05-04

Applicant: IBM ,  IBM UK ,  ARMSTRONG WILLIAM JOSEPH ,  ARNDT RICHARD LOUIS ,  CORRIGAN MICHAEL JOSEPH ,  ENGEBRETSEN DAVID ROBERT ,  MARCHINI TIMOTHY RICHARD ,  NAYAR NARESH

Inventor： ARMSTRONG WILLIAM JOSEPH ,  ARNDT RICHARD LOUIS ,  CORRIGAN MICHAEL JOSEPH ,  ENGEBRETSEN DAVID ROBERT ,  MARCHINI TIMOTHY RICHARD ,  NAYAR NARESH

IPC: G06F12/10

CPC classification number: G06F3/065 ,  G06F3/0611 ,  G06F3/0673 ,  G06F12/109

Abstract: Managing computer memory in a computer with dynamic logical partitioning that operates transparently with respect to operating systems in logical partitions. Exemplary methods, systems, and products are described for managing computer memory in a computer with dynamic logical partitioning that include copying by a hypervisor, from page frames in one logical memory block ("LMB") of a logical partition ("LPAR") to page frames outside the LMB, contents of page frames having page frame numbers in a page table for an operating system in the LPAR. Embodiments typically include storing new page frame numbers in the page table, including storing by the hypervisor, for each page frame whose contents are copied, a new page frame number that identifies the page frame to which contents are copied. In typical embodiments, copying contents of page frames and storing new page frame numbers are carried out transparently with respect to the operating system.

Abstract translation: 在具有相对于逻辑分区中的操作系统透明运行的动态逻辑分区的计算机中管理计算机内存。 描述了用于在具有动态逻辑划分的计算机中管理计算机存储器的示例性方法，系统和产品，其包括由管理程序从逻辑分区（“LPAR”）的一个逻辑存储块（“LMB”）中的页面帧到 在LMB之外的页框，在LPAR中的操作系统的页表中具有页框号的页框内容。 实施例通常包括在页面表中存储新的页面帧号码，包括由管理程序存储针对其内容被复制的每个页面帧的新的页面帧号码，其标识内容被复制到的页面帧。 在典型的实施例中，相对于操作系统透明地执行复印页面的内容和存储新的页面帧号码。

公开(公告)号：JP2007272885A

公开(公告)日：2007-10-18

申请号：JP2007071774

申请日：2007-03-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARNDT RICHARD LOUIS ,  THURBER STEVE MARK

IPC: G06F12/10 ,  G06F13/28

CPC classification number: G06F11/141 ,  G06F12/08 ,  G06F12/1081

Abstract: PROBLEM TO BE SOLVED: To provide a method for managing DMA-write page fault by a computer using a pool of substitute write buffer pages.
SOLUTION: A platform of a computer system solves the DMA-write page fault for a page exclusive to an I/O adapter. The I/O adapter attempts to write DMA data in the page, it is determined that the page is not usable for writing, and the DMA data are written into data locations in the substitute page selected from the pool of substitute pages. Then, a flag is set to a flag location corresponding to each of the data locations. The flag locations correspond to the data locations, and when the flags are set, the flags represent that the DMA data reside in the data locations corresponding to the flag locations of the flags.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过计算机使用替代写入缓冲器页面池管理DMA写入页面错误的方法。 解决方案：计算机系统的平台解决了I / O适配器专用页面的DMA写入页面错误。 I / O适配器尝试在页面中写入DMA数据，确定该页面不能用于写入，并且将DMA数据写入从替代页面池中选择的替代页面中的数据位置。 然后，将标志设置为对应于每个数据位置的标志位置。 标志位置对应于数据位置，并且当标志被设置时，标志表示DMA数据驻留在对应于标志的标志位置的数据位置中。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2009193590A

公开(公告)日：2009-08-27

申请号：JP2009055764

申请日：2009-03-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARNDT RICHARD LOUIS ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F12/14 ,  G06F9/46 ,  G06F13/36 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To provide a method, system, and apparatus for preventing input/output (I/O) used by an operating system (OS) image, in a logically partitioned data processing system, from corrupting or fetching data allocated to another OS image within the system. SOLUTION: This logically partitioned data processing system includes a plurality of logical partitions, the plurality of operating systems (OS), a plurality of memory locations, a plurality of I/O adapters (IOA), and a hypervisor. Each of the operating system images is assigned to each of different logical partitions. Each of the memory locations and each of the input/output adapters are assigned to one of the logical partitions. The hypervisor prevents transmission of data between the input/output adapter in one of the logical partitions and the memory location assigned to the other logical partition during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在逻辑分区的数据处理系统中防止操作系统（OS）图像使用的输入/输出（I / O）的方法，系统和装置，以破坏或获取数据 分配给系统中的另一个OS映像。 解决方案：该逻辑分区数据处理系统包括多个逻辑分区，多个操作系统（OS），多个存储器位置，多个I / O适配器（IOA）和管理程序。 每个操作系统映像被分配给每个不同的逻辑分区。 每个存储器位置和每个输入/输出适配器被分配给一个逻辑分区。 虚拟机管理程序防止在直接存储器访问（DMA）操作期间在逻辑分区之一的输入/输出适配器和分配给另一逻辑分区的存储器位置之间传输数据，通过将每个输入/输出适配器分配给I / O总线DMA地址。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006127524A

公开(公告)日：2006-05-18

申请号：JP2005313466

申请日：2005-10-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM JOSEPH ,  ARNDT RICHARD LOUIS ,  BENHASE MICHAEL THOMAS ,  BLOUNT LAWRENCE CARTER ,  HSU YU-CHENG ,  NAYAR NARESH

IPC: G06F9/50 ,  G06F9/46

CPC classification number: G06F9/5077 ,  G06F9/4881 ,  G06F2209/5014

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for managing access to a resource included in a data processing environment logically partitioned by a partition.
SOLUTION: This device, this program and this method assure a temporal period in which use of a resource by the partition is not forcibly excluded by a hypervisor. Inquiry communication transmitted by the partition urges the hypervisor to determine whether work for the hypervisor in a pending state or not. If not, the hypervisor transmits an assurance response for assuring the period of uninterrupted use of the resource by the partition.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于管理对由分区进行逻辑分区的数据处理环境中包括的资源的访问的改进方法。 解决方案：该设备，该程序和该方法确保了一个时间段，在该时间段内，分区的资源使用不被管理程序强制排除。 由分区发送的查询通信会敦促管理程序确定管理程序是否处于待处理状态。 如果没有，则管理程序发送保证响应，以确保分区不间断地使用资源的时间段。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE69419680T2

公开(公告)日：2000-03-02

申请号：DE69419680

申请日：1994-09-15

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNGS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/26

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：DE102016222127A1

公开(公告)日：2017-05-18

申请号：DE102016222127

申请日：2016-11-10

Applicant: IBM

Inventor： AUERNHAMMER FLORIAN ALEXANDER ,  ARNDT RICHARD LOUIS

IPC: G06F9/48

Abstract: Eine Technik zum Verarbeiten von Interrupts in einem Datenverarbeitungssystem beinhaltet ein Empfangen einer Ereignisbenachrichtigungsnachricht (Event Notification Message, ENM) in einer Interruptdarstellungs-Steuereinheit (Interrupt Presentation Controller, IPC). Die ENM gibt eine Ereigniszielnummer, eine Anzahl zu ignorierender Bits, eine Ereignisquellennummer und eine Ereignispriorität an. Die IPC ermittelt eine Gruppe virtueller Prozessor-Threads, die möglicherweise auf der Grundlage der Ereigniszielnummer und der in der ENM angegebenen Anzahl zu ignorierender Bits unterbrochen werden können. Die Ereigniszielnummer kennzeichnet einen bestimmten virtuellen Prozessor-Thread, und die Anzahl zu ignorierender Bits kennzeichnet die Anzahl von Bits niedrigerer Ordnung, die in Bezug auf den betreffenden virtuellen Prozessor-Thread zu ignorieren sind, wenn eine Gruppe virtueller Prozessor-Threads ermittelt wird, die möglicherweise unterbrochen werden können.

公开(公告)号：JP2012064215A

公开(公告)日：2012-03-29

申请号：JP2011202136

申请日：2011-09-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GILES ROGER FRASER ,  ARNDT RICHARD LOUIS ,  RONALD HALL

IPC: G06F11/30

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/485

Abstract: PROBLEM TO BE SOLVED: To provide a method, an information processing system, and a processor for tracking an activity of an assist hardware thread with the use of an assist thread status register by an initiating hardware thread without involvement of a supervisor program.SOLUTION: A processor 100 includes an initiating hardware thread 120 (initiating HT), and initiates a first assist hardware to execute a first code segment. Next, the initiating HT sets an assist thread executing indicator (ATI) in response to initiating a first assist hardware thread 150 (AHT). An AT indicates whether the AHT is executing or not. A second AHT is initiated and starts execution of a second code segment. Subsequently, the initiating HT detects a change in the ATI and evaluates an execution result of the AHT in response to process termination of both of the first AHT and the second AHT, which is indicated by the indicator.

Abstract translation: 要解决的问题：提供一种方法，信息处理系统和处理器，用于通过启动硬件线程使用辅助线程状态寄存器跟踪辅助硬件线程的活动，而不涉及主管程序 。 解决方案：处理器100包括启动硬件线程120（启动HT），并且启动第一辅助硬件以执行第一代码段。 接下来，启动HT响应于启动第一辅助硬件线程150（AHT）而设置辅助线程执行指示符（ATI）。 AT指示AHT是否执行。 第二个AHT被启动并开始执行第二个代码段。 随后，起始HT检测到ATI中的变化，并且响应于由指示符指示的第一AHT和第二AHT两者的过程终止来评估AHT的执行结果。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2004303237A

公开(公告)日：2004-10-28

申请号：JP2004085678

申请日：2004-03-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM J ,  ARNDT RICHARD LOUIS ,  NAYAR NARESH

IPC: G06F9/46 ,  G06F9/22 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F13/24

CPC classification number: G06F13/24 ,  G06F9/45541 ,  G06F9/4812 ,  G06F9/5077

Abstract: PROBLEM TO BE SOLVED: To support virtual interrupts in a computer system that may include share processors with no changes to a logical partition's operating system.
SOLUTION: A set of virtual interrupt registers is created for each virtual processor in the system. A resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the viewpoint of the operating system, the interrupt processing when the operating system is running in a logical partition that may include shared processors and virtual interrupts is no different from the interrupt processing when the operating system is running in the computer system that only includes dedicated processor partitions.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2003216592A

公开(公告)日：2003-07-31

申请号：JP2002275672

申请日：2002-09-20

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  CRADDOCK DAVID F ,  GREGG THOMAS A ,  JUDD IAN DAVID ,  PFISTER GREGORY FRANCIS ,  RECIO RENATO JOHN ,  DONALD WILLIAM SCHMIDT

IPC: G06F15/17 ,  G06F9/54 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide some optimizing techniques for sending a work request from a consumer to a channel adapter hardware, and method, device and program for sending a work completion to the consumer. SOLUTION: A distributed computing system having host and I/O end nodes, switches, routers and links interconnecting these components is provided. The end nodes use a pair of transmission/reception queues to transmit/receive messages. The end nodes use completion queues to inform the end user when messages have been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism for controlling the transfer of the work requests from the consumer to the channel adapter hardware by using only head pointers in the hardware is described. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002318701A

公开(公告)日：2002-10-31

申请号：JP2002010686

申请日：2002-01-18

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F12/14 ,  G06F9/46 ,  G06F13/36 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To prevent an I/O, which is to be used by one OS within a logically divided system, from destroying or fetching data belonging to the other OS within the system. SOLUTION: A hypervisor assigns an I/O bus direct memory access(DMA) address range to each of input/output adapters and prevents data from being transmitted between the input/output adapter inside one logic domain and a memory location assigned to the other logic domain during DMA operation. The I/O adapter(IOA) is connected through a terminal bridge to a PCI host bridge. A single terminal bridge can support a plurality of IOA as well, every terminal bridge has a plurality of sets of range registers, and each of sets is related to each of IOA. An arbiter is provided for selecting one of input/output adapters to use a PCI bus. The terminal bridge investigates a grant signal from the arbiter to the IOA and the set of range registers to be used is determined.