公开(公告)号：EP1875507A4

公开(公告)日：2009-08-05

申请号：EP06740000

申请日：2006-03-30

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

公开(公告)号：EP2024997A4

公开(公告)日：2009-12-16

申请号：EP07797486

申请日：2007-05-16

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2007131867B1

公开(公告)日：2008-03-06

申请号：PCT/EP2007054077

申请日：2007-04-25

Applicant: IBM ,  IBM UK ,  JAFFE MARK DAVID ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  KARTSCHOKE PAUL DAVID ,  STAMPER ANTHONY KENDALL ,  BERNSTEIN KERRY

Inventor： JAFFE MARK DAVID ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  KARTSCHOKE PAUL DAVID ,  STAMPER ANTHONY KENDALL ,  BERNSTEIN KERRY

IPC: H01L21/768 ,  H01L27/12

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract translation: 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二触点到器件 通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

公开(公告)号：WO02067425A2

公开(公告)日：2002-08-29

申请号：PCT/GB0200516

申请日：2002-02-07

Applicant: IBM ,  IBM UK

Inventor： BERNSTEIN KERRY ,  NOWAK EDWARD JOSEPH

IPC: H01L27/092 ,  H01L27/12 ,  H03K3/356

CPC classification number: H01L27/1203 ,  H01L27/0922 ,  H03K3/356113

Abstract: A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices is provided. Specifically, the differential circuit comprises an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gates that are used in cross-coupling.

Abstract translation: 提供了用作非对称双栅互补金属氧化物半导体（DGCMOS）器件的闭锁的差分电路。 具体地说，差分电路包括一个非对称DGCMOS器件，其具有连接到输入电路的弱栅极和用于交叉耦合的强栅极。

公开(公告)号：WO2006113077A3

公开(公告)日：2007-04-12

申请号：PCT/US2006011558

申请日：2006-03-30

Applicant: IBM ,  BERNSTEIN KERRY ,  SLEIGHT JEFFREY W ,  YANG MIN

Inventor： BERNSTEIN KERRY ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化从SOI和体硅区域FET的组合构建的电路的功率和性能。

公开(公告)号：WO2007137049A3

公开(公告)日：2008-01-31

申请号：PCT/US2007069002

申请日：2007-05-16

Applicant: IBM ,  BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.

Abstract translation: 一种半导体结构及其制造方法。 该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100​​B）去除后侧硅（110A和110B），并使用掩埋氧化物 层（115）。 接触件（210）然后在上晶片（I00B）中形成在下晶片（100A）中的器件（130A），并且布线层（170）形成在上晶片（100B）上。 下晶片（100A）可以包括布线​​层（170）。 下晶片（100A）可以包括用于触点的着陆焊盘（230）。 与下晶片（100A）的硅层（120）的接触可以被硅化。

公开(公告)号：DE60231792D1

公开(公告)日：2009-05-14

申请号：DE60231792

申请日：2002-02-07

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  NOWAK EDWARD JOSEPH

IPC: H03K3/356 ,  H01L27/092 ,  H01L27/12

Abstract: A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices. The differential circuit includes an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gates that are used in cross-coupling.

公开(公告)号：DE3789726T2

公开(公告)日：1994-11-24

申请号：DE3789726

申请日：1987-02-17

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  FURMAN ANATOL

IPC: G11C11/41 ,  G11C8/16 ,  G11C11/412 ,  G11C8/00

Abstract: A memory cell that allows simultaneous writing into the cell and reading from the cell includes a cross-coupled latch (10) in which two pairs of a load transistor (12, 14) and a pull-down transistor (20, 24) are connected at respective first and second coupling points (16, 18). However, the feedback path from the first coupling point (16) to the gate electrode of the pull-down transistor (24) of the other pair passes through a feedback transistor (30) which can thus selectively open this feedback path. In any access to the memory cell, the feedback path is interrupted. Any one of a plurality of write signals (WP1, WP2) can be impressed upon the gate electrode of the thus separated pull down transistor (24). Simultaneously, the signal on the first coupling point (16) can be selectively impressed upon any combination of a plurality of read lines (58, 60, 62). If a simultaneous writing and reading is being performed, the write signal passes immediately through the memory cell to the read lines.

公开(公告)号：DE3480445D1

公开(公告)日：1989-12-14

申请号：DE3480445

申请日：1984-05-09

Applicant: IBM

Inventor： BERNSTEIN KERRY

IPC: G11C11/417 ,  G11C7/00 ,  G11C8/16 ,  G11C8/18 ,  G11C8/20 ,  G11C11/41 ,  H01L27/10 ,  G11C8/00

公开(公告)号：AT427584T

公开(公告)日：2009-04-15

申请号：AT02712037

申请日：2002-02-07

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  NOWAK EDWARD

IPC: H03K3/356 ,  H01L27/092 ,  H01L27/12

Abstract: A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices. The differential circuit includes an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gates that are used in cross-coupling.