公开(公告)号：EP1683187A4

公开(公告)日：2008-08-27

申请号：EP04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：JP2012054555A

公开(公告)日：2012-03-15

申请号：JP2011187435

申请日：2011-08-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICKY S AMOS ,  BOYD DIANE C ,  CYRIL CABRAL JR ,  RICHARD D KAPLAN ,  JAKUB T KEDZIERSKI ,  VICTOR KU ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  ANNE L ZEUGEN ,  SERENDRA MAHESWARAN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal oxide semiconductor integration process that allows a plurality of silicide metal gates to be prepared on a gate dielectric.SOLUTION: There is provided a CMOS silicide metal gate integration method capable of eliminating a demerit of generation of variations in the height of poly Si gate stock which varies a silicide metal gate phase. The integration method minimizes the complexity of the process, thereby restraining the manufacturing cost of a CMOS transistor from increasing.

Abstract translation: 要解决的问题：提供允许在栅极电介质上制备多个硅化物金属栅极的互补金属氧化物半导体集成工艺。 解决方案：提供了一种CMOS硅化物金属栅极集成方法，其能够消除改变硅化物金属栅极相的多晶硅栅极原料的高度变化的缺点。 该集成方法最小化了工艺的复杂性，从而抑制了CMOS晶体管的制造成本增加。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JPH11317524A

公开(公告)日：1999-11-16

申请号：JP3111199

申请日：1999-02-09

Applicant: IBM

Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enable a field effect transistor to be accurately specified in channel length, lessened in source and drain resistance, and minimized in overlap capacitance, by a method wherein a gate hole is demarcated on a dielectric stack, an attached side wall layer is removed from a horizontal plane, and the gate hole is filled up with a gate conductor. SOLUTION: An etching window which is nearly equal in lateral dimension to a gate pillar that is specified in dimensions by a resist mask is provided to a dielectric stack which comprises nitride layers 31 and 38. An RIE process for forming a gate hole is used for transferring the etching window to the dielectric stack. Then, the gate hole is demarcated-by an RIE method, a side wall layer is attached and then removed from a horizontal plane. By this setup, the gate hole is lessened in length by a residual side wall spacer 61. Then, polysilicon is deposited inside the gate hole and on a dielectric stack uppermost layer 38, and the dielectric stack uppermost layer 38 is exposed by flattening the deposited polysilicon.

公开(公告)号：WO2005050701A8

公开(公告)日：2005-11-03

申请号：PCT/US2004037434

申请日：2004-11-09

Applicant: IBM ,  DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L21/8238 ,  H01L31/119 ,  H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L31/113

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate (1), providing an electrode (6) on the substrate (1), forming a recess (12) in the electrode (6), the recess having an opening, disposing a small grain semiconductor material (17) within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Abstract translation: 一种制造半导体器件结构的方法，包括：提供衬底（1），在所述衬底（1）上提供电极（6），在所述电极（6）中形成凹部（12），所述凹部具有开口， 在凹部内设置小晶粒半导体材料（17），在凹部内覆盖开口以容纳小晶粒半导体材料，然后对所得结构进行退火。

公开(公告)号：WO2007005145A3

公开(公告)日：2007-03-22

申请号：PCT/US2006020221

申请日：2006-05-25

Applicant: IBM ,  BOYD DIANE C ,  IEONG MEIKEI ,  KEDZIERSKI JAKUB TADEUSZ ,  SHAHIDI GHAVAM G

Inventor： BOYD DIANE C ,  IEONG MEIKEI ,  KEDZIERSKI JAKUB TADEUSZ ,  SHAHIDI GHAVAM G

IPC: H01L29/47 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/94 ,  H01L31/058

CPC classification number: H01L29/66643 ,  H01L29/66772 ,  H01L29/78654

Abstract: An ultra thin SOl MOSFET device structure and method of fabrication is presented. The device has a terminal (20) composed o suicide, which terminal is forming a Schottky contact with the channel (30). A plurality of impurities (70) are segregated on the silicide/channel interface (60), and these segregated impurities determine the resistance of the Schottky contact. Such impurity segregation is achieved by a so called silicidation induced impurity segregation process. Silicon substitutional impurities are appropriate for accomplishing such a segregation.

Abstract translation: 提出了一种超薄的SO1 MOSFET器件结构及其制造方法。 该装置具有由硅化物组成的端子（20），该端子与通道（30）形成肖特基接触。 多个杂质（70）被分离在硅化物/沟道界面（60）上，这些分离的杂质决定了肖特基接触的电阻。 这种杂质偏析通过所谓的硅化物诱导的杂质分离过程来实现。 硅替代杂质适合于实现这种分离。

公开(公告)号：WO2005083780A2

公开(公告)日：2005-09-09

申请号：PCT/US2005005565

申请日：2005-02-22

Applicant: IBM ,  AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

Inventor： AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

Abstract translation: 本发明提供了互补金属氧化物半导体集成工艺，由此在栅极电介质顶上制造多个硅化金属栅极。 不管硅化物金属栅极的尺寸如何，使用本发明的集成方案形成的每个硅化金属栅极具有相同的硅化物金属相和基本相同的高度。 本发明还提供了形成具有硅化触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：SG71909A1

公开(公告)日：2000-04-18

申请号：SG1999000606

申请日：1999-02-15

Applicant: IBM

Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78

Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.