公开(公告)号：US3701111A

公开(公告)日：1972-10-24

申请号：US3701111D

申请日：1971-02-08

Applicant: IBM

Inventor： COCKE JOHN ,  MOMMENS JACQUES H ,  RAVIV JOSEF

IPC: H03M7/40 ,  H03M7/42 ,  G06F7/00

CPC classification number: H03M7/4025 ,  H03M7/425

Abstract: This code conversion method enables data which has been coded in the form of variable-length bit strings for data compaction purposes to be processed by hardware units of conventional design that handle data in the form of fixed-length bit strings. The coding scheme is such that in the bit string of each variablelength code whose length exceeds a certain fixed number of bits N, the first N bits constitute a ''''length prefix'''' which uniquely designates the code length. This N-bit prefix is decoded by a first decoding table to give a base address in a second decoding table. The remaining bits of the variable-length code, whose number is known from the length prefix, then are decoded to give a displacement value relative to the base address for locating the address at which the decoded fixed-length word is found. Concurrently with the execution of this second decoding step, the first step in the decoding of the next variable-length code is performed. If a variable-length code does not have more than N bits, it is decoded in one step by the first decoding table, which stores the decoded word at every address therein which may be designated by all possible N-bit combinations containing the aforesaid variable-length code as their leading portion. A length indication read out of the first table then shifts the address register contents by an appropriate amount to bring the next succeeding variable-length code into the leading position therein.

Abstract translation: 该代码转换方法使得以用于数据压缩目的的可变长度比特串形式的数据能够以处理固定长度比特串形式的数据的常规设计的硬件单元来处理。 编码方案是这样的，即在长度超过某个固定数量的比特数N的每个可变长度码的比特串中，前N个比特构成唯一地指定码长的“长度前缀”。 该N比特前缀由第一解码表解码，以在第二解码表中给出基地址。 从长度前缀知道其可编号码的其余位然后被解码，以给出相对于基址的位移值，用于定位找到解码的固定长度字的地址。 与第二解码步骤的执行同时执行下一个可变长度码的解码的第一步骤。 如果可变长度码不超过N位，则通过第一解码表在一个步骤中解码，该第一解码表将解码字存储在其中可以由包含上述变量的所有可能的N位组合指定的每个地址 长度代码作为其主要部分。 从第一表读出的长度指示然后将地址寄存器内容移动适当的量，以使下一个后续的可变长度代码进入其中的前导位置。

公开(公告)号：US3577190A

公开(公告)日：1971-05-04

申请号：US3577190D

申请日：1968-06-26

Applicant: IBM

Inventor： COCKE JOHN ,  DAUBER PHILIP S ,  SCHORR HERBERT ,  SUSSENGUTH EDWARD H

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/10

CPC classification number: G06F9/30069

Abstract: Apparatus in a digital computer for allowing the skipping of predetermined instructions in a sequence of instructions is disclosed. Means are provided for detecting a specific type of instruction in a sequence of instructions. This specific type of instruction is referred to as a skip instruction and indicates that upon the occurrence of a specified machine condition, predetermined subsequent instructions in said sequence are to be skipped. Further means are provided to determine the occurrence of the specified machine condition, and to emit an output signal indicative of the occurrence. Means responsive to the output signal effect the skipping of the predetermined instructions.

公开(公告)号：US3527930A

公开(公告)日：1970-09-08

申请号：US3527930D

申请日：1967-07-19

Applicant: IBM

Inventor： COCKE JOHN ,  FREIMAN CHARLES V ,  HOMAN MERLE E

IPC: G06F7/52 ,  G06F7/535 ,  G06F7/38 ,  G06F7/44

CPC classification number: G06F7/535

公开(公告)号：US3577189A

公开(公告)日：1971-05-04

申请号：US3577189D

申请日：1969-01-15

Applicant: IBM

Inventor： COCKE JOHN ,  RANDELL BRIAN ,  SCHORR HERBERT ,  SUSSENGUTH EDWARD H

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/00 ,  G06F9/16

CPC classification number: G06F9/3846

Abstract: Apparatus and a method in a digital computer is disclosed for allowing improved program branching from a first instruction sequence to a second instruction sequence. Said apparatus includes means for decoding a branch instruction in said first sequence; means for determining parameters which are to enter into a condition determination, the resolution of which defines whether or not the branch is to be made, means for detecting a specific type instruction in said first sequence subsequent to said branch instruction, said specific type instruction indicative of the point in the first instruction sequence at which the branch is to be made; and means responsive to said detection for ordering instructions from said second instruction sequence to be processed subsequent to the processing of said specific type instruction.

公开(公告)号：US3427592A

公开(公告)日：1969-02-11

申请号：US3427592D

申请日：1964-11-12

Applicant: IBM

Inventor： BAHNSEN RALPH J ,  COCKE JOHN

IPC: G06F9/355 ,  G11B13/00

CPC classification number: G06F9/355

公开(公告)号：JPS6149242A

公开(公告)日：1986-03-11

申请号：JP17444185

申请日：1985-08-09

Applicant: Ibm

Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  MARKSTEIN PETER WILLY

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/443

公开(公告)号：DE68924477T2

公开(公告)日：1996-05-30

申请号：DE68924477

申请日：1989-12-12

Applicant: IBM

Inventor： COCKE JOHN ,  MONTOYE ROBERT KEVIN

IPC: G06F7/487 ,  G06F7/527 ,  G06F7/53 ,  G06F7/544 ,  G06F7/48

公开(公告)号：DE3851038D1

公开(公告)日：1994-09-15

申请号：DE3851038

申请日：1988-10-20

Applicant: IBM

Inventor： CHANG ALBERT ,  COCKE JOHN ,  MERGEN MARK FREDERICK ,  OEHLER RICHARD RAPHAEL

IPC: G06F12/00 ,  G06F12/14

Abstract: A method of and a controller for accessing a protected memory which is logically divided into major partitions - pages - which are in turn sub-divided into minor partitions - blocks - by concurrently executing transactions, using virtual block addressing and address translation at the memory controller via an access table, wherein there are provided table entries containing priviledged access control fields relating to the pages and lock fields relating to the individual blocks, by receiving an address of a data block to be accessed by an identifiable transaction; deriving from the address an access table entry corresponding to the data block and testing the data in the page access control field and the lock field governing access to the block; and providing the requested access if permitted by the access control data and the lock data for the type of access concerned, and also providing recorded access, if not permitted but not specifically denied by the lock data, using at least part of the lock field to record such latter type of access.

公开(公告)号：DE3485929T2

公开(公告)日：1993-04-01

申请号：DE3485929

申请日：1984-05-30

Applicant: IBM

Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  HAO HSIEH TUNG ,  MARKSTEIN PETER WILLY ,  RADIN GEORGE

IPC: G06F9/30 ,  G06F7/493 ,  G06F7/50 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32 ,  G06F9/46

Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

公开(公告)号：DE3481560D1

公开(公告)日：1990-04-12

申请号：DE3481560

申请日：1984-05-30

Applicant: IBM

Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  HAO HSIEH TUNG ,  MARKSTEIN PETER WILLY ,  RADIN GEORGE

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/32 ,  G06F9/48 ,  G06F9/46

Abstract: @ A mechanism for performing a run-time storage ad-dress validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry (52) for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.