公开(公告)号：EP1766691A4

公开(公告)日：2011-06-29

申请号：EP05732384

申请日：2005-03-30

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L31/113 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

公开(公告)号：EP1949447A4

公开(公告)日：2009-11-11

申请号：EP06825854

申请日：2006-10-12

Applicant: IBM

Inventor： CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

公开(公告)号：EP1825521A4

公开(公告)日：2008-10-01

申请号：EP05820881

申请日：2005-11-01

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

公开(公告)号：JP2006054465A

公开(公告)日：2006-02-23

申请号：JP2005233104

申请日：2005-08-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FRANK MARTIN M ,  REZNICEK ALEXANDER ,  GOUSEV EVGENI P ,  CARTIER EDUARD A

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/283

CPC classification number: H01L29/495 ,  H01L21/76254 ,  H01L21/823828 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To provide a technique for forming a gate stack partially at least on a semiconductor substrate which makes it possible to use various gate materials without sacrificing device performance.
SOLUTION: There is provided the method of forming a gate stack for a semiconductor electron device using the wafer bonding of at least one structure containing a high k dielectric material. The method comprises a step of selecting first and second structures each having a principal plane. At least one of or both of the first and the second structures comprise the high k dielectric material at least. Then, a bonding structure comprising at least the high k dielectric material of the gate stack is formed by joining the primary planes of the first and the second structures.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供至少部分地在半导体衬底上形成栅叠层的技术，这使得可以在不牺牲器件性能的情况下使用各种栅极材料。 解决方案：提供了使用包含高k电介质材料的至少一种结构的晶片接合形成半导体电子器件的栅极堆叠的方法。 该方法包括选择具有主平面的第一和第二结构的步骤。 第一和第二结构中的至少一个或两者至少包括高k电介质材料。 然后，通过连接第一和第二结构的主平面来形成至少包括栅叠层的高k电介质材料的键合结构。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003051549A

公开(公告)日：2003-02-21

申请号：JP2002162321

申请日：2002-06-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BALLANTINE ARNE W ,  BUCHANAN DOUGLAS A ,  CARTIER EDUARD A ,  COOLBAUGH DOUGLAS D ,  GOUSEV EVGENI P ,  OKORN-SCHMIDT HARALD F

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/28 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/51 ,  H01L29/94

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide an FEOL capacitor such as a polysilicon-polysilicon capacitor and an MIS capacitor wherein high permittivity (high-k) dielectrics whose permittivity k is higher than about 8 can be assembled in a capacitor structure, and a method for manufacturing the FEOL capacitor.
SOLUTION: First, a lower electrode 12 is formed in an Si containing substrate 10 by using ion implantation. The high permittivity dielectrics 14 whose permittivity k is higher than about 8 is formed on at least a part of the lower electrode 12. A doped Si containing electrode 16 of a bipolar device constituted of an intrinsic base polysilicon layer is formed on the high permittivity dielectrics 14. By performing the above processes, an MIS capacitor can be obtained. By the method, the FEOL capacitor wherein the upper and the lower electrode in which series resistance is small are formed, capacitance per unit area is large, and high frequency response characteristic is superior can be obtained. Further, chip size can be reduced remarkably, and especially in the use of an analog signal and a mixed signal in which a capacitor of large area is used, chip size can be reduced remarkably.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了提供诸如多晶硅 - 多晶硅电容器和MIS电容器的FEOL电容器，其电容率k高于约8的高介电常数（高k）电介质可以组装在电容器结构中，以及用于 制造FEOL电容。 解决方案：首先，通过使用离子注入在含Si衬底10中形成下电极12。 介电常数k大于约8的高介电常数电介质14形成在下电极12的至少一部分上。由高介电常数电介质形成由本征基极多晶硅层构成的双极器件的掺杂Si含电极16 通过执行上述处理，可以获得MIS电容器。 通过该方法，形成其中串联电阻小的上电极和下电极的FEOL电容器，每单位面积的电容量大，并且可以获得高的频率响应特性。 此外，芯片尺寸可以显着降低，特别是在使用大面积的电容器的模拟信号和混合信号的使用中，芯片尺寸可以显着降低。

公开(公告)号：WO2005122286A3

公开(公告)日：2009-04-16

申请号：PCT/US2005010825

申请日：2005-03-30

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprisisng an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be A1N or A1OxNY. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HC1/H2O2 peroxide solution.

Abstract translation: 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在半导体衬底顶部形成介电堆叠，其中包括在高k电介质顶部的绝缘夹层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极叠层。 绝缘中间层可以是AlN或AlOxNY。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HC1 / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：WO2006055226A3

公开(公告)日：2007-08-23

申请号：PCT/US2005039288

申请日：2005-11-01

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Abstract translation: 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，其条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。

公开(公告)号：WO2007050312A2

公开(公告)日：2007-05-03

申请号：PCT/US2006039940

申请日：2006-10-12

Applicant: IBM ,  CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

Inventor： CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO 2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

Abstract translation: 一种半导体结构，特别是pFET，其包括具有大于SiO 2的介电常数和大于50％的Ge或Si含量的介电常数的介电材料和至少一种用于 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。