公开(公告)号：EP1766691A4

公开(公告)日：2011-06-29

申请号：EP05732384

申请日：2005-03-30

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L31/113 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

公开(公告)号：EP1949447A4

公开(公告)日：2009-11-11

申请号：EP06825854

申请日：2006-10-12

Applicant: IBM

Inventor： CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

公开(公告)号：EP1872407A4

公开(公告)日：2011-09-14

申请号：EP06750529

申请日：2006-04-18

Applicant: IBM

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823842

公开(公告)号：WO2005122286A3

公开(公告)日：2009-04-16

申请号：PCT/US2005010825

申请日：2005-03-30

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprisisng an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be A1N or A1OxNY. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HC1/H2O2 peroxide solution.

Abstract translation: 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在半导体衬底顶部形成介电堆叠，其中包括在高k电介质顶部的绝缘夹层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极叠层。 绝缘中间层可以是AlN或AlOxNY。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HC1 / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：WO2007050312A2

公开(公告)日：2007-05-03

申请号：PCT/US2006039940

申请日：2006-10-12

Applicant: IBM ,  CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

Inventor： CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO 2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

Abstract translation: 一种半导体结构，特别是pFET，其包括具有大于SiO 2的介电常数和大于50％的Ge或Si含量的介电常数的介电材料和至少一种用于 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：WO2006115894A2

公开(公告)日：2006-11-02

申请号：PCT/US2006014516

申请日：2006-04-18

Applicant: IBM ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L29/76

CPC classification number: H01L21/823842

Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

Abstract translation: 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。