中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.017 seconds)

    High-performance cmos circuit, and manufacturing method therefor
    3.
    发明专利
    High-performance cmos circuit, and manufacturing method therefor 有权
    高性能CMOS电路及其制造方法

    公开(公告)号：JP2007184583A

    公开(公告)日：2007-07-19

    申请号：JP2006343524

    申请日：2006-12-20

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： VIJAY NARAYANAN ,  VAMSI K PARUCHURI ,  CHEN TZE-CHIANG ,  ALESSANDRO CALLEGARI ,  JOSEPH S NEWBURY ,  MICHELLE L STEEN ,  DORIS BRUCE B ,  MICHAEL PATRIK CHUDZIK ,  LINDER BARRY P ,  JOHN C ARNOLD

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

    CPC classification number: H01L21/823857 ,  H01L21/823842

    Abstract: PROBLEM TO BE SOLVED: To provide a CMOS circuit which includes an n-FET gate stack having a gate dielectric and a metal gate conductor, and a p-FET gate stack having a gate dielectric layer and a silicon-containing gate conductor. SOLUTION: In the high-performance complementary metal oxide film semiconductor (CMOS) circuit, each semiconductor unit has at least the first gate stack and the second gate stack. The first gate stack is disposed on a first device region (e.g., n-FET device region) in a semiconductor board, and at least includes a gate dielectric layer 14, a metal gate conductor 16, and a silicon-containing gate conductor 18 that are laminated in increasing order. The second gate stack is disposed on a second device region (e.g., p-FET device region) in the semiconductor board; and at least includes a gate dielectric layer, and a silicon-containing gate conductor that are laminated in increasing order. The first and second gate stacks can be formed on the semiconductor board by a variety of integrated methods. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 解决的问题：提供一种CMOS电路，其包括具有栅极电介质和金属栅极导体的n-FET栅极堆叠，以及具有栅极介电层和含硅栅极导体的p-FET栅极堆叠 。 解决方案：在高性能互补金属氧化物半导体（CMOS）电路中，每个半导体单元至少具有第一栅极堆叠和第二栅极堆叠。 第一栅极堆叠设置在半导体板中的第一器件区域（例如，n-FET器件区域）上，并且至少包括栅极电介质层14，金属栅极导体16和含硅栅极导体18， 以增加的顺序层压。 第二栅极堆叠设置在半导体板中的第二器件区域（例如，p-FET器件区域）上; 并且至少包括以增加的顺序层叠的栅极介电层和含硅栅极导体。 第一和第二栅极堆叠可以通过各种集成方法形成在半导体板上。 版权所有（C）2007，JPO＆INPIT

    USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES
    6.
    发明申请
    USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES 审中-公开
    使用金属/金属氮化物双层作为自对准的标准CMOS器件中的栅极电极

    公开(公告)号：WO2006115894A2

    公开(公告)日：2006-11-02

    申请号：PCT/US2006014516

    申请日：2006-04-18

    Applicant: IBM ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

    Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

    IPC: H01L29/76

    CPC classification number: H01L21/823842

    Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

    Abstract translation: 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

Patent Agency Ranking