公开(公告)号：EP1846947A4

公开(公告)日：2009-04-15

申请号：EP05852630

申请日：2005-12-02

Applicant: IBM

Inventor： VEREECKEN PHILIPPE M ,  BASKER VEERARAGHAVAN ,  CABRAL CYRIL JR ,  COOPER EMANUEL I ,  DELIGIANNI HARIKLIA ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  PARUCHURI VAMSI KRISHNA ,  SAENGER KATHERINE L ,  SHAO XIAOYAN

IPC: H01L21/302 ,  H01L29/745

CPC classification number: H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

Abstract: A method for electroplating a gate metal (9) or other conducting or semiconducting material on a gate dielectric (2) is provided. The method involves selecting a substrate (3, 4), dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be generated at an interface between the dielectric layer and the electrolyte solution or melt.

公开(公告)号：EP1766691A4

公开(公告)日：2011-06-29

申请号：EP05732384

申请日：2005-03-30

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L31/113 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

公开(公告)号：EP1949447A4

公开(公告)日：2009-11-11

申请号：EP06825854

申请日：2006-10-12

Applicant: IBM

Inventor： CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

公开(公告)号：EP1825521A4

公开(公告)日：2008-10-01

申请号：EP05820881

申请日：2005-11-01

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

公开(公告)号：EP1836732A4

公开(公告)日：2009-07-01

申请号：EP05826298

申请日：2005-12-02

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

公开(公告)号：JP2005328059A

公开(公告)日：2005-11-24

申请号：JP2005139334

申请日：2005-05-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BOJARCZUK NESTOR A JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI ,  SUPURATEIKU GUUHA ,  NARAYANAN VIJAY

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L21/28202 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide semiconductor (CMOS) structure including an intermediate layer between a Si-containing gate electrode and a high-k gate dielectric, so that a threshold voltage and a flat-band voltage of the structure are stabilized.
SOLUTION: An insulating intermediate layer for use in the complementary metal-oxide semiconductor (CMOS) is provided in order to prevent undesirable shifts of the threshold voltage and the flat-band voltage. The insulating intermediate layer is disposed between a gate dielectric having a dielectric constant of more than 4.0 and a Si-containing gate conductor. The insulating intermediate layer comprises metal nitride capable of containing oxygen, and stabilizes the threshold voltage and the flat-band voltage. For a preferred embodiment, the insulating intermediate layer comprises aluminum nitride or aluminum oxinitride, and the gate dielectric comprises a hafnium oxide, hafnium silicate, or hafnium oxinitride. The structure is especially useful for stabilizing the threshold voltage and the flat-band voltage of a p-type field effect transistor.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供在含Si栅极电极和高k栅极电介质之间包括中间层的互补金属氧化物半导体（CMOS）结构，使得阈值电压和平带电压 的结构是稳定的。 解决方案：提供用于互补金属氧化物半导体（CMOS）的绝缘中间层，以便防止阈值电压和平带电压的不希望的偏移。 绝缘中间层设置在介电常数大于4.0的栅极电介质和含Si的栅极导体之间​​。 绝缘中间层包括能够含有氧的金属氮化物，稳定阈值电压和平带电压。 对于优选实施例，绝缘中间层包括氮化铝或氮氧化铝，栅极电介质包括氧化铪，硅酸铪或氧化铪。 该结构对于稳定p型场效应晶体管的阈值电压和平带电压特别有用。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2005122286A3

公开(公告)日：2009-04-16

申请号：PCT/US2005010825

申请日：2005-03-30

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprisisng an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be A1N or A1OxNY. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HC1/H2O2 peroxide solution.

Abstract translation: 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在半导体衬底顶部形成介电堆叠，其中包括在高k电介质顶部的绝缘夹层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极叠层。 绝缘中间层可以是AlN或AlOxNY。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HC1 / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：WO2006076087A2

公开(公告)日：2006-07-20

申请号：PCT/US2005043555

申请日：2005-12-02

Applicant: IBM ,  CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

Inventor： CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

IPC: H01L29/94

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

Abstract translation: 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）的高温下退火HfSiN /高k电介质/界面层之后，界面层的减少，因此栅叠层产生非常小的等效氧化物厚度 （12经典），使用TaSiN无法实现。

公开(公告)号：JP2011003899A

公开(公告)日：2011-01-06

申请号：JP2010136861

申请日：2010-06-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDO TAKASHI ,  CHOI CHANGHWAN ,  NARAYANAN VIJAY ,  FRANK MARTIN M

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: PROBLEM TO BE SOLVED: To provide a high-k gate dielectric which maintains a constant threshold voltage even after a high temperature process in a CMOS integration step.SOLUTION: A stack of a high-k gate dielectric 30 and a metal gate structure including a lower metal layer 40, a capture metal layer 50, and an upper metal layer 60 is provided. The capture metal layer satisfies the following two standards: (1) to be a metal (M) which indicates a positive change in Gibbs free energy caused by a reaction of Si+2/yMO→2x/yM+SiO; and (2) to be a metal the Gibbs free energy of which is a larger negative value than a metal of the lower metal layer and a metal of the upper metal layer per oxygen atom to form an oxide. The capture metal layer satisfying these standards captures oxide atoms when the oxide atoms pass through a gate electrode, to be diffused toward the high-k gate dielectric. Furthermore, the capture metal layer reduces a thickness of a silicon oxide interface layer under the high-k gate dielectric remotely. As a result, a change in equivalent oxide thickness (EOT) of the whole gate dielectric is controlled.

Abstract translation: 要解决的问题：提供即使在CMOS集成步骤中的高温处理之后仍保持恒定的阈值电压的高k栅极电介质。解决方案：高k栅极电介质30和金属栅极结构的堆叠包括 提供下金属层40，捕获金属层50和上金属层60。 捕获金属层满足以下两个标准：（1）作为表示由Si + 2 / yMO→2x / yM + SiO的反应引起的吉布斯自由能的正变化的金属（M） 和（2）作为金属，其吉布斯自由能比下金属层的金属和每个氧原子的上金属层的金属具有更大的负值，以形成氧化物。 当氧化物原子通过栅电极时，满足这些标准的捕获金属层捕获氧化物原子，以朝向高k栅极电介质扩散。 此外，捕获金属层远离了高k栅极电介质下的氧化硅界面层的厚度。 结果，控制了整个栅极电介质的等效氧化物厚度（EOT）的变化。

公开(公告)号：JP2007123895A

公开(公告)日：2007-05-17

申请号：JP2006290473

申请日：2006-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FRANK MARTIN M ,  HUILING SHANG ,  KOESTER STEVEN JOHN ,  OTT JOHN ALBRECHT

IPC: H01L29/161 ,  H01L21/283 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/02052 ,  H01L21/02046 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure, capable of obtaining a germanium system semiconductor device, such as FET and MOS capacitor.
SOLUTION: More specifically, the method for forming the semiconductor device, containing a stack consisting of a dielectric layer and a conductive material on the surface being an upper section or an internal section of a germanium contained material in which a non-oxygen chalcogen is rich (layer or wafer) or both of them is provided. The density of an interface trap is decreased, because undesirable formations of interface compounds at the time of growing the dielectric and thereafter is suppressed, by providing interfaces in which the non-oxygen chalcogen is rich.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供能够获得诸如FET和MOS电容器的锗系统半导体器件的方法和结构。 解决方案：更具体地，在表面上包含由电介质层和导电材料构成的叠层的半导体器件的形成方法，其是含锗材料的上部或内部部分，其中非氧 硫族元素丰富（层或晶片），或者都提供它们。 界面陷阱的密度降低，因为通过提供其中非氧硫属元素富的界面，在电介质生长时不期望的界面化合物的形成被抑制。 版权所有（C）2007，JPO＆INPIT