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    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT
    2.
    发明公开
    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT 有权
    VERWENDUNG REDUNDANTER ROUTEN ZURVERGRÖSSERUNGVON AUSBEUTE UNDZUVERLÄSSIGKEITEINES VLSI-LAYOUTS

    公开(公告)号：EP1889194A4

    公开(公告)日：2008-10-01

    申请号：EP06760106

    申请日：2006-05-18

    Applicant: IBM

    Inventor： BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5068

    Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

    Abstract translation: 公开了一种用于将冗余路径（40,50）插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于识别连接两个元件的第一路径（40）中的单个通孔（30）的方法，确定替代路线是否可用于连接两个元件（10,20）（不同于冗余通孔 54）），并且用于将第二路径（50）插入到可用的替代路线（70）中。 第一路径（40）和第二路径（50）的组合提供比单独插入冗余通路（54）更大的冗余。 更重要的是，这种冗余路径（50）在拥塞阻止冗余通路（54）被插入邻近单个通路（30）时提供冗余。 如果可以使用于形成第二路径的所有附加通路（52）变得冗余，则该方法的实施例还包括移除单个通路（30）和任何冗余导线段（51）。

    Yield optimization in router for systematic defect
    3.
    发明专利
    Yield optimization in router for systematic defect 有权
    系统缺陷路由器的优化优化

    公开(公告)号：JP2007311773A

    公开(公告)日：2007-11-29

    申请号：JP2007101249

    申请日：2007-04-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BICKFORD JEANNE P ,  BUEHLER MARKUS ,  HIBBELER JASON D ,  KOEHL JUERGEN ,  MAYNARD DANIEL N

    IPC: H01L21/82 ,  H01L21/66

    CPC classification number: G06F17/5077

    Abstract: PROBLEM TO BE SOLVED: To provide a method which optimize router settings so as to improve IC yield, and to provide a computer program product. SOLUTION: Yield data in an IC manufacturing line are reviewed so as to identify structure-specific mechanisms that impact the IC yield. Next, with respect to each structure-specific mechanism, a structural identifier including a wire code, a tag and/or unique identifiers is established. With respect to a wire having different width, the structural identifier is established. Subsequently, the weighting factor is established for each structure-specific mechanism in such a way that a higher weighting factor is established with respect to a structure-specific mechanism including a thick wire which is the most proximate to multiple thick wires. The structural identifier and the weighting factor with respect to the spacing produced between single width lines, double width lines, and triple width lines and wires arranged on a large metal land. Then, the router settings are modified based on the structural identifier and the weighting factor so as to minimize systematic defects. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种优化路由器设置以提高IC产量并提供计算机程序产品的方法。 解决方案：审查IC生产线中的产量数据，以便识别影响IC产量的结构特异性机制。 接下来，关于每个结构特定机制，建立包括有线代码，标签和/或唯一标识符的结构标识符。 对于具有不同宽度的导线，建立了结构标识符。 随后，针对每个结构特定机构建立加权因子，使得相对于包括最接近多个粗线的粗线的结构特定机构建立较高的加权因子。 单个宽度线，双宽度线和三条宽度线之间产生的间距的结构标识符和加权因子以及排列在大金属地面上的导线。 然后，基于结构标识符和权重因子修改路由器设置，以便最小化系统缺陷。 版权所有（C）2008，JPO＆INPIT

    Integrated circuit routing specification method and program
    4.
    发明专利
    Integrated circuit routing specification method and program 有权
    集成电路路由规范方法和程序

    公开(公告)号：JP2007158340A

    公开(公告)日：2007-06-21

    申请号：JP2006326345

    申请日：2006-12-01

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： COHN JOHN M ,  HIBBELER JASON D ,  TELLEZ GUSTAVO E

    IPC: H01L21/82 ,  G06F17/50

    CPC classification number: G06F17/5077

    Abstract: PROBLEM TO BE SOLVED: To provide the method of implementing yield recognition IC route specification for designing, and to provide a computer program.
    SOLUTION: In this method, an early global routing for satisfying wiring congestion constraint is implemented. Then, in this method, wire spreading and wire widening are implemented per layer with respect to global routing, based on, for example, the second congestion optimization. Subsequently, the timing convergence is implemented for global routing by using the result of wire spreading and wire widening. Then, the adjustment of wiring width after routing and wire spreading is carried out by using a critical area yield model. Furthermore, this method enables optimization of already routed data.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供实现产量识别IC路由规范的设计方法，并提供计算机程序。 解决方案：在这种方法中，实现了用于满足布线拥塞约束的早期全局路由。 然后，在这种方法中，基于例如第二拥塞优化，相对于全局路由，每层实施有线扩展和线拓宽。 随后，通过使用线扩展和线宽扩展的结果，实现了全局路由的定时收敛。 然后，通过使用临界区域产量模型来进行布线和布线扩展之后的布线宽度的调整。 此外，该方法能够优化已经路由的数据。 版权所有（C）2007，JPO＆INPIT

    INTEGRATED CIRCUIT SELECTIVE SCALING
    5.
    发明申请
    INTEGRATED CIRCUIT SELECTIVE SCALING 审中-公开
    集成电路选择性标定

    公开(公告)号：WO2006044730A2

    公开(公告)日：2006-04-27

    申请号：PCT/US2005037145

    申请日：2005-10-14

    Applicant: IBM ,  HENG FOOK-LUEN ,  HIBBELER JASON D ,  MCCULLEN KEVIN W ,  NARAYAN RANI R ,  RUNYON STEPHEN L ,  WALKER ROBERT F

    Inventor： HENG FOOK-LUEN ,  HIBBELER JASON D ,  MCCULLEN KEVIN W ,  NARAYAN RANI R ,  RUNYON STEPHEN L ,  WALKER ROBERT F

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: Methods, systems and program products are disclosed for selectively scaling (100) an integrated circuit (IC) design (200): by layer, by unit, or by ground rule, or a combination of these (130). The selective scaling technique can be applied in a feedback loop (408) with the manufacturing system (400) with process and yield feedback (300), during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

    Abstract translation: 公开了用于根据层，单元或基础规则或这些的组合（130）选择性地缩放（100）集成电路（IC）设计（200）的方法，系统和程序产品。 选择性缩放技术可以在设计寿命期间与制造系统（400）一起在反馈回路（408）中应用于具有处理和产量反馈（300）的反馈回路（408）中，以提高早期处理中的产量，使得分级结构 保存。 本发明消除了在实现诸如无掩模制造的新技术的情况下涉及设计人员提高产量的需要。

    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT
    6.
    发明申请
    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT 审中-公开
    使用冗余路由增加VLSI布局的可靠性

    公开(公告)号：WO2006125091A2

    公开(公告)日：2006-11-23

    申请号：PCT/US2006019257

    申请日：2006-05-18

    Applicant: IBM ,  BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

    Inventor： BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5068

    Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

    Abstract translation: 公开了一种用于将冗余路径（40,50）插入到集成电路中的方法和系统。 特别地，本发明提供一种用于在连接两个元件的第一路径（40）中识别单个通孔（30）的方法，确定替代路径是否可用于连接两个元件（10,20）（除了冗余通孔 54）），并且用于将第二路径（50）插入到可用替代路线（70）中。 第一（40）和第二路径（50）的组合提供比单独插入冗余通路（54）更大的冗余。 更重要的是，当拥塞阻止冗余通路（54）相邻于单通道（30）插入时，这种冗余路径（50）提供冗余。 如果用于形成第二路径的所有附加通孔（52）可以是冗余的，则该方法的实施例还包括移除单个通孔（30）和任何冗余线段（51）。

    7.
    发明专利
    未知

    公开(公告)号：DE602006006567D1

    公开(公告)日：2009-06-10

    申请号：DE602006006567

    申请日：2006-05-18

    Applicant: IBM

    Inventor： BUEHLER MARKUS T ,  COHN JOHN M OLD JONES ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

    IPC: G06F17/50

    Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

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