公开(公告)号：JPH06169565A

公开(公告)日：1994-06-14

申请号：JP35066891

申请日：1991-12-12

Applicant: IBM

Inventor： CHI RIAN CHIEN ,  SAN HOO DON ,  HIYUN JIYON SHIN

IPC: G11C11/407 ,  G05F1/56 ,  H02M3/07

Abstract: PURPOSE: To apply differential amplifiers to a small drop-out voltage regulator and improve power source elimination, by connecting a series regulating element with the outputs of the differential amplifiers, making a source-follower and constituting a booster of the differential amplifiers with voltage pump circuits. CONSTITUTION: A series regulating element MN1 connected with the outputs of differential amplifiers MN2-MN4 and MP1-MP2 acts as source-follower. A booster (booster VCC) INT of the differential amplifiers MN2-MN4 and MP1-MP2 is constituted of voltage pump circuits MP4-MP6, CRUMP1-CRUMP2, CSTORE. Gate potentials of the differential amplifiers MN2-MN4 and MP1-MP2 are increased with the voltage pump circuits MP4-MP6, CRUMP1-CRUMP2, CSTORE. Thereby, the differential amplifiers can be applied to a small drop-out voltage regulator, power source elimination can be improved, and lower external power source sensitivity can be obtained.

公开(公告)号：JPH0629824A

公开(公告)日：1994-02-04

申请号：JP6154093

申请日：1993-03-22

Applicant: IBM

Inventor： SHIYANGU HOO DONGU ,  HIYUN JIYON SHIN

IPC: H03K19/013 ,  H03K19/018 ,  H03K19/0944

Abstract: PURPOSE: To make the shift of a signal sure at an output by switching a prearranged signal at an output terminal in accordance with the change of an input signal. CONSTITUTION: A circuit 20 is driven by using an input on a line T from a logical block 22. In the circuit 20, feedback control is performed from an active type signal pull-up stage to a pull-down stage through a diode D1, and a signal switching shift stage is driven. When a signal on the line T increases from L to H, the voltage drop VBE of an Q1 increases, the voltage at a point Z rapidly falls, next, the voltage at a point Y rapidly increases, the pull-down current of an Q2 drops and a signal quickly increases at an OUTPUT. The VBE and collector current returns to stableness, associated with the increase of an output, and a push-pull operation is stopped. When a signal on the line T falls from H to L, the VBE reduces, the voltage of the point Z increases, and current of the Q2 and output discharge current sharply increases.

公开(公告)号：JPH06343036A

公开(公告)日：1994-12-13

申请号：JP30385991

申请日：1991-10-24

Applicant: IBM

Inventor： CHINNTE KENTO CHIYAN ,  HIYUN JIYON SHIN

IPC: H03K17/00 ,  H03K17/62 ,  H03K19/086

Abstract: PURPOSE: To provide a high-speed multiplexer circuit with which the number of semiconductors to be used is minimized. CONSTITUTION: The high-speed multiplexer circuit is provided with plural input bipolar transistors 16 and a reference bipolar transistor 32. Concerning the input and reference transistors 16 and 32, their emitters are commonly coupled to an emitter current source 36 and their collectors are coupled to a collector power source 18. The collector of reference transistor 32 is coupled through an impedance 40 to the collector power source 18. The reference voltage is connected to the base of reference bipolar transistor 32 and applies a bias for conduction. Input signals to be multiplexed are connected to the respective bases of input bipolar transistors 16 and between the bases of respective input bipolar transistors 16 and a switch input, a diode circuit 26 is coupled. In the first state, the switch input conducts this diode circuit, clamps the base of this input transistor and prevents that transistor from responding to a signal input.

公开(公告)号：JPH04130823A

公开(公告)日：1992-05-01

申请号：JP41579590

申请日：1990-12-28

Applicant: IBM

Inventor： CHINNTE KENTO CHIYUAN ,  HIYUN JIYON SHIN

IPC: H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H03K17/567 ,  H03K19/01 ,  H03K19/013 ,  H03K19/086

Abstract: PURPOSE: To improve the switching speed of a whole ECL device by connecting a junction field effect transistor(FET) with a pull-up circuit in one line and adjusting the depression area of the standard gate of the transistor(FET) so as to decrease or increase the conductivity between the source and drain of the FET. CONSTITUTION: A back gate 14 is provided so as to provide additional conducting path adjustment for further controlling the overall impedance of the ECL device during switching operations between the source 9 and drain 13 of a junction FET. The back gate 14 of the junction FET is connected to a preceding logical stage 25 and switched by gate connection. While the output logical state is switched from logic '1' to logic '2', the impedance of a pull- down device 30 is dropped in the initial stage for modulating the back gate 14 connected to a depression area limited by a standard gate and an N-type well 8. The instantaneous drop of the impedance increases the current flowing to the drain from the source and quickly discharges the potential at a load connecting section.

公开(公告)号：JPH0865147A

公开(公告)日：1996-03-08

申请号：JP17573395

申请日：1995-07-12

Applicant: IBM

Inventor： SUDEIIRU MANISUWAMII GOUDA ,  HIYUN JIYON SHIN ,  KEBUIN ROBAATO RENAA

IPC: G11C11/407 ,  H02M3/07 ,  H03K19/0948

Abstract: PROBLEM TO BE SOLVED: To obtain the charge pump circuit which generates an output voltage substantially double as high as its input voltage without causing a voltage drop by a switching device. SOLUTION: A charge pump including 1st and 2nd precharge/boost circuits 2 and 4 switches a p-MOSFET switching device P13 so as to hold a certain voltage level which is double as large as the input without causing any discharge (leak) of charges. The 1st precharge/boost circuit 2 includes a p-MOSFET switch P11 which is connected to a power source VDD and an inverter I66 which has its output connected to the gate of a switch P11. The 2nd precharge/boost circuit 4 includes a p-MOSFET switch P21 connected to the power source VDD and a NAND gate I68 having its output connected to the gate of the switch P21.

公开(公告)号：JPH06223572A

公开(公告)日：1994-08-12

申请号：JP24806793

申请日：1993-10-04

Applicant: IBM

Inventor： SAN HOO DONGU ,  KIRIHATA TOSHIAKI ,  HIYUN JIYON SHIN ,  SUNANAGA TOSHIO ,  TAIRA YOICHI ,  RUISU MADEISON TERUMAN

IPC: G11C11/409 ,  G11C11/407 ,  G11C11/4094

Abstract: PURPOSE: To reduce the power dissipating amounts of a bit line by providing a DRAM structure using a variable precharge voltage detecting technique. CONSTITUTION: In the end of a row address storage(RAS) cycle, a bit line 10 and a complementary bit 12 are short-circuited, and short-circuited through a line 32 with VEQ by equalizing devices 18, 20, and 22, and balancing is operated by bit line precharge in the next RAS cycle. This voltage is higher than the precharge voltage in the previous cycle. When a capacitance 88 of a memory cell to which access is performed stores 0V, the bit line precharge voltage is made lower than that in the previous RAS cycle. When a high level is stored in the cell capacitance of the cell connected with a word line and accessed in each following cycle, the same sequence is repeated in the following RAS cycle, and the bit line precharge voltage is increased in each cycle. Then, a bit line power can not be drawn from a DRAM power source by the balancing with a bit line pair voltage.

公开(公告)号：JPH05198176A

公开(公告)日：1993-08-06

申请号：JP21703692

申请日：1992-08-14

Applicant: IBM

Inventor： SAN FUU DON ,  HIYUN JIYON SHIN ,  UEI WAN

IPC: G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  H01L21/822 ,  H01L27/04

Abstract: PURPOSE: To provide a regulator relaxing an electric field on a thin oxide at a word line driver and a circuit related to it, in a worst case without giving adversely affecting the response time of a memory array. CONSTITUTION: The voltage regulator is provided with a band gap reference regulator 30, a first differential amplifier 34 generating a transition voltage from a reference voltage, a first transistor comparing the power source voltage and a boosting voltage, a second transistor comparing the transition voltage and the reference voltage and a latching comparator 44 equalizing outputs from the first and second transistors, so as to define a control signal for an on-chip generator.