公开(公告)号：DE3677665D1

公开(公告)日：1991-04-04

申请号：DE3677665

申请日：1986-07-25

Applicant: IBM

Inventor： BRUNSVOLD WILLIAM R ,  CONLEY WILLARD E ,  JACOBS SCOTT L ,  MACK GEORGE L ,  MERRIT DAVID P ,  UPTMOR ANN M

IPC: C08L79/08 ,  C08K5/13 ,  C08K5/1545 ,  G03F7/004 ,  G03F7/037 ,  G03F7/09 ,  G03F7/11 ,  G03F7/26

公开(公告)号：CA1277434C

公开(公告)日：1990-12-04

申请号：CA534157

申请日：1987-04-08

Applicant: IBM

Inventor： JACOBS SCOTT L ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI D ,  ZINGHER ARTHUR R

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538

Abstract: MODULE FOR PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT CHIPS ON A BASE SUBSTRATE An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connect the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each have coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed; low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.

公开(公告)号：CA2002213A1

公开(公告)日：1990-05-10

申请号：CA2002213

申请日：1989-11-03

Applicant: MICROELECTRONICS CENTER OF NOR ,  IBM ,  NORTHERN TELECOM LTD

Inventor： TURLIK IWONA ,  REISMAN ARNOLD ,  NAYAK DEEPAK ,  HWANG LIH-TYNG ,  DISHON GIORA ,  JACOBS SCOTT L ,  DARVEAUX ROBERT F ,  POLEY NEIL M

IPC: H01L23/373 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H01L23/34

Abstract: A high performance integrated circuit chip package (10) includes a support (15) substrate (12) having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate (16) on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink (26) with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The multilayer wiring substrate (16) may be formed by a self-aligned thin film wiring method, with a self-aligned lift off method being employed to form internal wiring planes. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

公开(公告)号：BR8702439A

公开(公告)日：1988-02-23

申请号：BR8702439

申请日：1987-05-13

Applicant: IBM

Inventor： JACOBS SCOTT L ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI D ,  ZINGHER ARTHUR R

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H01L23/30

Abstract: An integrated circuit chip packaging structure, preferably having a semiconductor base substrate (1), i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers (8) being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connect the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each have coplanar ground, power (39, 40) and signal lines (19, 20), with at least one power (16) or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed, low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.

公开(公告)号：CA2002213C

公开(公告)日：1999-03-30

申请号：CA2002213

申请日：1989-11-03

Applicant: NORTHERN TELECOM LTD ,  IBM ,  MCNC

Inventor： TURLIK IWONA ,  REISMAN ARNOLD ,  NAYAK DEEPAK ,  HWANG LIH-TYNG ,  DISHON GIORA ,  JACOBS SCOTT L ,  DARVEAUX ROBERT FRANCIS ,  POLEY NEIL M

IPC: H01L23/373 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H01L23/34

Abstract: A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The multilayer wiring substrate may be formed by a self-aligned thin film wiring method, with a self-aligned lift off method being employed to form internal wiring planes. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

公开(公告)号：CA1266148A

公开(公告)日：1990-02-20

申请号：CA499386

申请日：1986-01-10

Applicant: IBM

Inventor： BABICH EDWARD D ,  HATZAKIS MICHAEL ,  JACOBS SCOTT L ,  PARASCZCAK JURI R ,  SHAW JANE M ,  WITMAN DAVID F

IPC: C08L61/00 ,  C08K5/549 ,  C08L33/00 ,  C08L33/02 ,  C08L61/04 ,  C08L61/06 ,  G03C1/00 ,  G03C1/72 ,  G03F7/004 ,  G03F7/038 ,  G03F7/26 ,  G03F7/38 ,  H01L21/027

Abstract: PLASMA-RESISTANT POLYMERIC MATERIAL, PREPARATION THEREOF, AND USE THEREOF Plasma-resistant polymeric materials are prepared by reacting a polymeric material containing reactive hydrogen functional groups with a multifunctional organometallic material containing at least two functional groups which are reactive with the reactive hydrogen functional groups of the polymeric material, such as hexamethylcyclotrisilazane.