公开(公告)号：EP0814175A2

公开(公告)日：1997-12-29

申请号：EP97304018

申请日：1997-06-10

Applicant: IBM

Inventor： REDDY SRINIVASA S N ,  KNICKERBOCKER JOHN ULRICH ,  WALL DONALD RENE

IPC: C23C16/08 ,  C23C16/44 ,  H01L21/28 ,  H01L21/285 ,  H05K3/24

CPC classification number: C23C16/08 ,  C23C16/44 ,  H05K3/244 ,  Y10T428/12944 ,  Y10T428/12965

Abstract: The present invention discloses a CVD (Chemical Vapor Deposition) process where nickel or alloys thereof, such as, Ni/Cu, Ni/Co, are deposited on metal surfaces (32, 34) which are capable of receiving nickel or alloys thereof, using an Iodide source (23), preferably an Iodide salt, such as, Copper Iodide.

Abstract translation: 本发明公开了一种CVD（化学气相沉积）方法，其中镍或其合金如Ni / Cu，Ni / Co沉积在能够接收镍或其合金的金属表面（32,34）上，使用 碘化物源（23），优选碘化物盐，例如碘化铜。

公开(公告)号：JP2002134926A

公开(公告)日：2002-05-10

申请号：JP2001193284

申请日：2001-06-26

Applicant: IBM

Inventor： DANIEL GEORGE BERGER ,  FAROOQ SHAJI ,  HERRON LESTER WYNN ,  HUMENIK JAMES N ,  KNICKERBOCKER JOHN ULRICH ,  PASCO ROBERT WILLIAM ,  PERRY CHARLES H ,  SACHDEV KRISHNA G

IPC: G02B6/12 ,  B32B18/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H05K1/03 ,  H05K1/05 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an organic inorganic compound electronic substrate which can be manufactured at a low cost, a compound electronic substrate wherein relative permitivity, impedance, CTE, double refraction and mutual connection stress are low, and package card reliability is high, a compound electronic substrate wherein Tg is high and thermal stability is superior, and a compound electronic substrate having low hygroscopicity. SOLUTION: A compound electronic and/or optical substrate contains polymer material and ceramic material, and has relative permitivity lower than 4 and coefficient of thermal expansion of 8-14 ppm/ deg.C at 100 deg.C. This compound substrate is composed of polymer material containing ceramic filler material or ceramic material containing polymer filler material.

公开(公告)号：WO2008100324A9

公开(公告)日：2009-05-22

申请号：PCT/US2007071370

申请日：2007-06-15

Applicant: IBM ,  EMMA PHILIP GEORGE ,  KNICKERBOCKER JOHN ULRICH ,  PATEL CHIRAG S

Inventor： EMMA PHILIP GEORGE ,  KNICKERBOCKER JOHN ULRICH ,  PATEL CHIRAG S

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.

Abstract translation: 更具体地说，一种电子计算的方法，更具体地说，一种设计三维芯片中的高速缓存层级的方法，以及由此产生的高速缓存层级，包括在三维实现的高速缓存层级中的位的物理布置，使得在 连接层次结构级别的总线最小化。 以这种方式，电平之间的数据路径主要是通孔本身，这导致非常短的，因此快速和低功率总线。

公开(公告)号：WO2008100324A3

公开(公告)日：2011-01-13

申请号：PCT/US2007071370

申请日：2007-06-15

Applicant: IBM ,  EMMA PHILIP GEORGE ,  KNICKERBOCKER JOHN ULRICH ,  PATEL CHIRAG S

Inventor： EMMA PHILIP GEORGE ,  KNICKERBOCKER JOHN ULRICH ,  PATEL CHIRAG S

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.

Abstract translation: 更具体地说，一种电子计算的方法，更具体地说，一种设计三维芯片中的高速缓存层级的方法，以及由此产生的高速缓存层级，包括在三维实现的高速缓存层级中的位的物理布置，使得在 连接层次结构级别的总线最小化。 以这种方式，电平之间的数据路径主要是通孔本身，这导致非常短的，因此快速和低功率总线。

公开(公告)号：JP2000040477A

公开(公告)日：2000-02-08

申请号：JP19719599

申请日：1999-07-12

Applicant: IBM

Inventor： BEETESON JOHN STUART ,  KNICKERBOCKER JOHN ULRICH ,  KNOX ANDREW RAMSAY ,  LOWE ANTHONY CYRIL

IPC: H01J1/46 ,  H01J3/02 ,  H01J29/02 ,  H01J29/46 ,  H01J29/68 ,  H01J31/12

Abstract: PROBLEM TO BE SOLVED: To provide such an electron source that an extracted current density coincides with an emission characteristic of a cathode and there is no interaction between a pixel/array structural part and an extracting grid. SOLUTION: A frame 202 is provided around an extracting grid 200. The extracting grid 200 comprises plural apertures 204, 207. The apertures 204 are etched and have a square shape. The smaller number of apertures 207 have a U-shape. Portions which are not removed from the extracting grid 200 form flap 206 areas. The flaps are mechanically bent at a right angle, to form the extracting grid 200 into a three-dimensional structure from a two-dimensional structure. The flaps 200 are used for precisely separating the extracting grid 200 from a cathode substrate 102. Thereby, the distance between the electron source and the extracting grid 200 can be kept constant.

公开(公告)号：JPH1187116A

公开(公告)日：1999-03-30

申请号：JP12380198

申请日：1998-05-06

Applicant: IBM

Inventor： KNICKERBOCKER JOHN ULRICH ,  KNOX ANDREW RAMSAY ,  ROSENBERG ROBERT

IPC: H01F1/00 ,  H01F7/02 ,  H01F41/16 ,  H01J29/68

Abstract: PROBLEM TO BE SOLVED: To provide a metal/ferrite laminated magnet having openings which are accurately aligned with a phosphor under all operating conditions by substantially aligning the openings of a first and second ferrite sheet with those of a second metallic plate. SOLUTION: A metallic plate 105 is cut to measure and openings 125 are formed through the plate 105 by etching. Then a first green ferrite sheet 115 is fitted to one surface of the etched metallic plate 105 and openings 125 are formed through the sheet 115 by punching by using the etched holes of the metallic plate 105 as guides. Openings 125 are also formed through a second metallic plate 110 and a second green ferrite sheet 120 in the same ways. Then a sandwich-like magnet 100 is formed by bringing the surfaces of the first and second green ferrite sheets 115 and 120 into contact with each other, coupling the sheets 115 and 120 with each other so that the opening of the sheets 115 and 120 may be aligned with each other, and sintering the laminated body. A vertically arranged magnetic field is given to the magnet 100.

公开(公告)号：JPH1116878A

公开(公告)日：1999-01-22

申请号：JP15962198

申请日：1998-06-08

Applicant: IBM

Inventor： KRISHUNA GANDE SACHIDEF ,  UMAA MOEZU UDEIN AMADO ,  KNICKERBOCKER JOHN ULRICH ,  CHON CHEON REI

IPC: C11D7/26 ,  C11D7/50 ,  C11D11/00 ,  H01L21/304 ,  H01L21/48 ,  H05K3/26

Abstract: PROBLEM TO BE SOLVED: To effectively remove flux residue of rosin base formed during high temperature solder reflow by using at least one non-halogenation/non-aromatic solvent as solvent when washing residue off at least one surface of a semiconductor device. SOLUTION: In a solvent washing process for washing residue off at least one surface of a semiconductor device, at least one non-halogenation/non- aromatic solvent is used as solvent. A solvent having at least two functional groups comprising that expressed by -OH and -COOR, -OR and -COOR, -OH and -OR, -OR and -OCOR [R is expressed by CnH2n+1 (n=1 to 4)] is suitable. Embodiments of the washing solvent are lactic ester, alkoxyalkyl ester, propylene glycol ether alkoxylate and that selected from a combination thereof.

公开(公告)号：JPH1068075A

公开(公告)日：1998-03-10

申请号：JP16163997

申请日：1997-06-18

Applicant: IBM

Inventor： REDDY SRINIVASA S N ,  KNICKERBOCKER JOHN ULRICH ,  WALL DONALD RENE

IPC: C23C16/08 ,  C23C16/44 ,  H01L21/28 ,  H01L21/285 ,  H05K3/24

Abstract: PROBLEM TO BE SOLVED: To deposit Ni or an Ni alloy on the surface of a metal hard to be worked by interposing an iodine material. SOLUTION: A metal 32 hard to be worked which is the exposed end part where Mo or the like is exposed on a ceramic base 30, depositing metallic materials 40 and 45 such as Ni or Ni alloy and solid iodine, preferably. CuI salt are charged into a box, is heated to about 700 to 1000 deg.C and is held for about 1 to 200min. The CuI 23 is brought into reaction with solid Ni or Ni alloy 40 and 45 in a vapor phase state to generate gaseous Ni iodine, which is brought into reaction with the exposed surface of the metal 32. Then, Ni molecules are reduced, and substantially pure Ni is deposited thereon. The iodine is made free from the metal 32, returned to the materials 40 and 45 and again brought into reaction with Ni, and the process is repeated. In this way, the iodine is used as a simple carrier for Ni and is not consumed in the process.

公开(公告)号：DE69806542D1

公开(公告)日：2002-08-22

申请号：DE69806542

申请日：1998-04-27

Applicant: IBM

Inventor： KNICKERBOCKER JOHN ULRICH ,  KNOX ANDREW RAMSAY ,  ROSENBERG ROBERT ,  HUMENIK JAMES N

IPC: H01F7/02 ,  H01F41/16 ,  H01J29/68 ,  H01F41/02

公开(公告)号：DE69708388T2

公开(公告)日：2002-08-08

申请号：DE69708388

申请日：1997-06-10

Applicant: IBM

Inventor： REDDY SRINIVASA S N ,  KNICKERBOCKER JOHN ULRICH ,  WALL DONALD RENE

IPC: C23C16/08 ,  C23C16/44 ,  H01L21/28 ,  H01L21/285 ,  H05K3/24

Abstract: The present invention discloses a CVD (Chemical Vapor Deposition) process where nickel or alloys thereof, such as, Ni/Cu, Ni/Co, are deposited on metal surfaces (32, 34) which are capable of receiving nickel or alloys thereof, using an Iodide source (23), preferably an Iodide salt, such as, Copper Iodide.