公开(公告)号：JPH11274380A

公开(公告)日：1999-10-08

申请号：JP1653899

申请日：1999-01-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： FAROOQ SHAJI ,  MARIO J INTARANTE ,  SDIPTA K RAY ,  WILLIAM E SABURINSKI

IPC: H01L23/32 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/0272 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To make a bonding part sufficiently strong, and prevent structural completeness from being lost in the subsequent reflow process, by making the melting point of a second solder bond at one edge of a connector lower than that at the other edge. SOLUTION: In an assembled interconnecting structure with a completed column grid array, an interconnecting structure (column) composed of an element with other shape such as a spherical shape is connected to an electronic module board 4 and a circuit card 10 via a land 17. The other edge of the column is connected to the land 17 of the circuit card 10, by the use of a Pb/Sn eutectic solder 17 (second solder bond), which has a lower melting point than that of a transient melting solder bonding part 3. The melting point of the eutectic solder 18 is normally 200 deg.C or below. The connection is achieved by the transient melting solder bonding part 3, which contains fine metal powder additive and is used for mounting the column on an input/output pad 5 on the board 4.

Abstract translation: 要解决的问题：通过使连接器的一个边缘处的第二焊接点的熔点低于另一个边缘的熔点，使接合部分足够强，并且防止结构完整性在随后的回流工艺中丢失。 解决方案：在具有完整的列格栅阵列的组装的互连结构中，由具有诸如球形的其他形状的元件组成的互连结构（列）经由焊盘17连接到电子模块板4和电路卡10。 该列的另一个边缘通过使用具有比瞬时熔融焊接部分的熔点低的熔点的Pb / Sn共晶焊料17（第二焊料接合）连接到电路卡10的焊盘17上 共晶焊料18的熔点通常为200℃以下。 该连接是通过瞬态熔融焊接部3实现的，该焊接接合部3含有细金属粉末添加剂，并用于将该列安装在板4上的输入/输出焊盘5上。

公开(公告)号：JPH11274407A

公开(公告)日：1999-10-08

申请号：JP3290499

申请日：1999-02-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： MAKUTA S FALUKE ,  FAROOQ SHAJI ,  HARVEY C HAMMEL ,  KNICKERBOCKER JOHN U ,  ROBERT A LITA ,  HERBERT I STOLER

IPC: H01L27/04 ,  H01G4/30 ,  H01G4/33 ,  H01L21/02 ,  H01L21/822

CPC classification number: H01L28/40 ,  H01G4/306 ,  Y10T29/435

Abstract: PROBLEM TO BE SOLVED: To provide an electronic component structure in which an interposer thin film capacitor structure is used between an electronic component and a multilayered circuit card. SOLUTION: In order to prevent the occurrence of fatal electric short circuits in an upper thin film area due to pits, voids, undulations on the surface of a substrate, a first metallic layer 5 having a thickness of about 0.5 μm to 10 μm is formed on the substrate and a thin film containing a dielectric film 6 and a second metallic film is formed on the metallic layer 5. The first metallic layer 5 is composed of Pt, another electrode metal, or a combination of Pt, Cr, Cu metal, and a diffusion barrier layer. In order to increase the adhesive power of the layer 5, an additional Ti layer can be used. The thicknesses of the Cr layer, Cu layer, diffusion barrier layer, and Pt layer constituting the first metallic layer 5 are respectively adjusted to about 200 Å, between about 0.5 μm and about 10 μm, between about 1,000 Å and about 5,000 Å and between about 100 Å and about 2,500 Å.

Abstract translation: 要解决的问题：提供一种在电子部件和多层电路卡之间使用中介层薄膜电容器结构的电子部件结构。 解决方案：为了防止由于基板表面上的凹坑，空隙，波纹引起的上部薄膜区域中的致命电短路，形成厚度为约0.5μm至10μm的第一金属层5 在金属层5上形成含有介电膜6和第二金属膜的薄膜。第一金属层5由Pt，另一种电极金属或Pt，Cr，Cu金属， 和扩散阻挡层。 为了增加层5的粘合力，可以使用另外的Ti层。 构成第一金属层5的Cr层，Cu层，扩散阻挡层和Pt层的厚度分别调节为约200，约0.5μm和约10μm之间，介于约至约5000之间和介于 约100埃和约2,500埃。

公开(公告)号：JP2002134926A

公开(公告)日：2002-05-10

申请号：JP2001193284

申请日：2001-06-26

Applicant: IBM

Inventor： DANIEL GEORGE BERGER ,  FAROOQ SHAJI ,  HERRON LESTER WYNN ,  HUMENIK JAMES N ,  KNICKERBOCKER JOHN ULRICH ,  PASCO ROBERT WILLIAM ,  PERRY CHARLES H ,  SACHDEV KRISHNA G

IPC: G02B6/12 ,  B32B18/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H05K1/03 ,  H05K1/05 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an organic inorganic compound electronic substrate which can be manufactured at a low cost, a compound electronic substrate wherein relative permitivity, impedance, CTE, double refraction and mutual connection stress are low, and package card reliability is high, a compound electronic substrate wherein Tg is high and thermal stability is superior, and a compound electronic substrate having low hygroscopicity. SOLUTION: A compound electronic and/or optical substrate contains polymer material and ceramic material, and has relative permitivity lower than 4 and coefficient of thermal expansion of 8-14 ppm/ deg.C at 100 deg.C. This compound substrate is composed of polymer material containing ceramic filler material or ceramic material containing polymer filler material.

公开(公告)号：DE69208675D1

公开(公告)日：1996-04-04

申请号：DE69208675

申请日：1992-06-23

Applicant: IBM

Inventor： AOUDE FARID ,  DAVID LAWRENCE ,  DIVAKARUNI RENUKA SHASTRI ,  FAROOQ SHAJI ,  HERRON LESTER ,  LASKY HAL ,  MASTREANI ANTHONY ,  NATARAJAN GOVINDARAJAN ,  REDDY SRINIVASA ,  SURA VIVEK MADAN ,  VALLABHANENI RAO ,  WALL DONALD RENE

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/46 ,  H01B1/02 ,  H01B1/16

Abstract: A copper-based paste is disclosed for filling vias in, and forming conductive surface patterns on, ceramic substrate packages for semiconductor chip devices. The paste contains copper aluminate powder in proper particle size and weight proportion to achieve grain size and shrinkage control of the via and thick film copper produced by sintering. The shrinkage of the copper material during sintering is closely matched to that of the ceramic substrate.

公开(公告)号：CA2072727A1

公开(公告)日：1993-03-11

申请号：CA2072727

申请日：1992-06-29

Applicant: IBM

Inventor： AOUDE FARID Y ,  DAVID LAWRENCE D ,  DIVAKARUNI RENUKA S ,  FAROOQ SHAJI ,  HERRON LESTER W ,  LASKY HAL M ,  MASTREANI ANTHONY ,  NATARAJAN GOVINDARAJAN ,  REDDY SRINIVASA S N ,  SURA VIVEK M ,  VALLABHANENI RAO V ,  WALL DONALD R

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/46 ,  H01B1/02

Abstract: FI9-90-027 COPPER-BASED PASTE CONTAINING COPPER ALUMINATE FOR MICROSTRUCTURAL AND SHRINKAGE CONTROL OF COPPER-FILLED VIAS A copper-based paste is disclosed for filling vias in, and forming conductive surface patterns on, ceramic substrate packages for semiconductor chip devices. The paste contains copper aluminate powder in proper particle size and weight proportion to achieve grain size and shrinkage control of the via and thick film copper produced by sintering. The shrinkage of the copper material during sintering is closely matched to that of the ceramic substrate.

公开(公告)号：MY117336A

公开(公告)日：2004-06-30

申请号：MYPI20012928

申请日：2001-06-21

Applicant: IBM

Inventor： BERGER DANIEL GEORGE ,  FAROOQ SHAJI ,  HERRON LESTER WYNN ,  HUMENIK JAMES N ,  KNICKERBOCKER JOHN ULRICH ,  PASCO ROBERT WILLIAM ,  PERRY CHARLES H ,  SACHDEV KRISHNA G

IPC: B32B5/16 ,  B32B18/00 ,  G02B6/12 ,  G02B6/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H05K1/03 ,  H05K1/05 ,  H05K3/46

Abstract: A COMPOSITE ELECTRONIC AND/OR OPTICAL SUBSTRATE INCLUDING POLYMERIC AND CERAMIC MATERIAL WHEREIN THE COMPOSITE SUBSTRATE HAS A DIELECTRIC CONSTANT LESS THAN 4 AND A COEFFICIENT OF THERMAL EXPANSION OF 8 TO 14 PPM/°C AT 100°C. THE COMPOSITE SUBSTRATE MAY BE EITHER CERAMIC-FILLED POLYMERIC MATERIAL OR POLYMER-FILLED CERAMIC MATERIAL. (FIGURE 1)

公开(公告)号：DE69208675T2

公开(公告)日：1996-09-26

申请号：DE69208675

申请日：1992-06-23

Applicant: IBM

Inventor： AOUDE FARID ,  DAVID LAWRENCE ,  DIVAKARUNI RENUKA SHASTRI ,  FAROOQ SHAJI ,  HERRON LESTER ,  LASKY HAL ,  MASTREANI ANTHONY ,  NATARAJAN GOVINDARAJAN ,  REDDY SRINIVASA ,  SURA VIVEK MADAN ,  VALLABHANENI RAO ,  WALL DONALD RENE

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/46 ,  H01B1/02 ,  H01B1/16

Abstract: A copper-based paste is disclosed for filling vias in, and forming conductive surface patterns on, ceramic substrate packages for semiconductor chip devices. The paste contains copper aluminate powder in proper particle size and weight proportion to achieve grain size and shrinkage control of the via and thick film copper produced by sintering. The shrinkage of the copper material during sintering is closely matched to that of the ceramic substrate.

公开(公告)号：BR9203415A

公开(公告)日：1993-04-13

申请号：BR9203415

申请日：1992-09-01

Applicant: IBM

Inventor： AOUDE FARID YOUSSIF ,  DAVID LAWRENCE D ,  DIVAKARUNI RENUKA S ,  FAROOQ SHAJI ,  HERRON LESTER W

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/46 ,  C04B41/38

Abstract: A copper-based paste is disclosed for filling vias in, and forming conductive surface patterns on, ceramic substrate packages for semiconductor chip devices. The paste contains copper aluminate powder in proper particle size and weight proportion to achieve grain size and shrinkage control of the via and thick film copper produced by sintering. The shrinkage of the copper material during sintering is closely matched to that of the ceramic substrate.