公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：WO2004053926A3

公开(公告)日：2004-11-25

申请号：PCT/EP0350958

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： MALHOTRA SANDRA ,  SIMON ANDREW

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a dielectric layer (18). The dielectric layer is patterned so as to expose the metal conductor. A liner layer (24) is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor (14). In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer (26) is deposited into the pattern and covers the redeposited liner layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被介电层（18）覆盖。 图案化电介质层以暴露金属导体。 然后将衬垫层（24）沉积到图案中。 然后对衬垫层进行氩溅射蚀刻以去除衬里层并暴露金属导体（14）。 在氩溅射蚀刻的过程中，衬里层被再沉积到图案的侧壁上。 最后，附加层（26）沉积到图案中并覆盖再沉积的衬里层。

公开(公告)号：WO2011084339A3

公开(公告)日：2011-09-09

申请号：PCT/US2010059607

申请日：2010-12-09

Applicant: IBM ,  FRYE ASA ,  SIMON ANDREW

Inventor： FRYE ASA ,  SIMON ANDREW

IPC: H01L21/336 ,  H01L21/24 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L29/665

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers (105, 106) over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) (100) through a physical vapor deposition (PVD) process, wherein the first metal layer (105) is deposited using a first nickel target material containing platinum (Pt), and the second metal layer (106) is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel- silicide layer (107) at a top surface of the gate, source, and drain regions.

Abstract translation: 本发明的实施例提供一种形成硅化镍的方法。 该方法可以包括通过物理气相沉积（PVD）在场效应晶体管（FET）（100）的栅极，源极和漏极区域中的至少一个上沉积第一和第二金属层（105,106） ）工艺，其中使用包含铂（Pt）的第一镍靶材料沉积第一金属层（105），并且使用不含第二金属层的第二镍靶材料将第二金属层（106）沉积在第一金属层的顶部 或更少的铂; 以及退火覆盖所述FET的所述第一和第二金属层，以在所述栅极，源极和漏极区域的顶表面处形成含铂的硅化镍层（107）。

公开(公告)号：GB2491935B

公开(公告)日：2013-09-04

申请号：GB201208149

申请日：2010-12-09

Applicant: IBM

Inventor： FRYE ASA ,  SIMON ANDREW

IPC: H01L21/285 ,  H01L29/66

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

公开(公告)号：AU2003300263A1

公开(公告)日：2004-06-30

申请号：AU2003300263

申请日：2003-12-08

Applicant: IBM

Inventor： MALHOTRA SANDRA ,  SIMON ANDREW

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/4763 ,  H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.

公开(公告)号：AU2003300263A8

公开(公告)日：2004-06-30

申请号：AU2003300263

申请日：2003-12-08

Applicant: IBM

Inventor： MALHOTRA SANDRA ,  SIMON ANDREW

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/4763 ,  H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.

公开(公告)号：AU2003298347A1

公开(公告)日：2004-06-30

申请号：AU2003298347

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  TULIPE DOUGLAS JR LA ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：DE112010004400T5

公开(公告)日：2012-12-20

申请号：DE112010004400

申请日：2010-12-09

Applicant: IBM

Inventor： SIMON ANDREW ,  FRYE ASA

IPC: H01L21/285 ,  H01L21/24 ,  H01L21/336 ,  H01L29/78

Abstract: In Ausführungsformen der Erfindung wird ein Verfahren zum Bilden von Nickelsilicid bereitgestellt. Das Verfahren kann das Abscheiden einer ersten und zweiten Metallschicht (105, 106) über zumindest einer aus einer Gate-, einer Source- und einer Drain-Zone eines Feldeffekttransistors (FET) (100) durch ein Verfahren der physikalischen Abscheidung aus der Gasphase (PVD) umfassen, wobei die erste Metallschicht (105) unter Verwendung eines ersten Nickel-Targetmaterials abgeschieden wird, welches Platin (Pt) enthält, und die zweite Metallschicht (106) unter Verwendung eines zweiten Nickel-Targetmaterials oben auf der ersten Metallschicht abgeschieden wird, welches kein Platin oder weniger Platin als das erste Nickel-Targetmaterial enthält; und das Tempern der ersten und zweiten Metallschicht umfassen, die den FET bedecken, um an einer oberen Fläche der Gate-, Source- und Drain-Zone eine platinhaltige Nickelsilicidschicht (107) zu bilden.

公开(公告)号：DE60332865D1

公开(公告)日：2010-07-15

申请号：DE60332865

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

公开(公告)号：AT470237T

公开(公告)日：2010-06-15

申请号：AT03796085

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.