公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：JP2004200684A

公开(公告)日：2004-07-15

申请号：JP2003413888

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN SHYNG-TSONG ,  DALTON TIMOTHY J ,  DAVIS KENNETH M ,  HU CHAO-KUN ,  JAMIN FEN F ,  KALDOR STEFFEN K ,  KRISHNAN MAHADEVAIYER ,  KUMAR KAUSHIK ,  MICHAEL F ROFARO ,  SANDRA G MARUHOTORA

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide the structure of an integrated circuit having a logic/functional device layer and an interconnection layer above it. SOLUTION: This interconnection layer has a substrate, a conductive feature 122 in the substrate, and a cap 151 which is formed only above the conductive feature. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：AU2003298347A1

公开(公告)日：2004-06-30

申请号：AU2003298347

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  TULIPE DOUGLAS JR LA ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：DE60332865D1

公开(公告)日：2010-07-15

申请号：DE60332865

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

公开(公告)号：AT470237T

公开(公告)日：2010-06-15

申请号：AT03796085

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：DE102004028026B4

公开(公告)日：2006-08-10

申请号：DE102004028026

申请日：2004-06-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUMAR KAUSHIK ,  CLEVENGER LARRY ,  DALTON TIMOTHY J ,  LA TULIPE DOUGLAS C ,  COWLEY ANDY ,  KALTALIOGLU ERDEM ,  SCHACHT JOCHEN ,  HOINKIS MARK ,  SIMON ANDREW H ,  KALDOR STEFFEN ,  YANG CHIH-CHAO

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

公开(公告)号：DE102004028026A1

公开(公告)日：2005-02-03

申请号：DE102004028026

申请日：2004-06-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUMAR KAUSHIK ,  CLEVENGER LARRY ,  DALTON TIMOTHY J ,  LA TULIPE DOUGLAS C ,  COWLEY ANDY ,  KALTALIOGLU ERDEM ,  SCHACHT JOCHEN ,  HOINKIS MARK ,  SIMON ANDREW H ,  KALDOR STEFFEN ,  YANG CHIH-CHAO

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3213