公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：JP2004158851A

公开(公告)日：2004-06-03

申请号：JP2003359944

申请日：2003-10-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LARRY ,  KLEPEIS STANLEY ,  LU HSIAO-LING ,  MARINO JEFFREY ,  SIMON ANDREW HERBERT ,  WANG YUN-YU ,  WONG KWONG HON ,  YANG CHIH-CHAO

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To solve the problem of carbon contamination that dos not occur in circuits using oxide as dielectric, which exists in advanced technology using low-k organic-based interlayer dielectrics in copper backend integrated circuit technology. SOLUTION: A composite liner layer for the copper lines uses Ti as a bottom layer, which has property of gettering carbon and other contaminants. The known problem of Ti as reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper. COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2004027824A2

公开(公告)日：2004-04-01

申请号：PCT/US0329085

申请日：2003-09-16

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV ,  CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE

Inventor： SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV ,  CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L

CPC classification number: H01L21/7685 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L2221/1078

Abstract: A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

Abstract translation: 提供了集成电路（12）中的导电结构以及形成该结构的方法，该导电结构包括多晶硅层（30），在多晶硅上包含钛的薄层，在钛 - 氮化镓层上的氮化钨层（34） 在氮化钨层上形成含钨层和钨层。 该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。 该结构耐受高温处理而在多晶硅层（30）和钨层（32）中基本上不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

公开(公告)号：JP2000100822A

公开(公告)日：2000-04-07

申请号：JP26415999

申请日：1999-09-17

Applicant: IBM ,  SIEMENS AG

Inventor： CLEVENGER LARRY ,  FILIPPI JR RONALD G ,  GAMBINO JEFFREY ,  GIGNAC LYNNE ,  HURD JEFFERY L ,  HOINKIS MARK ,  IGGULDEN ROY C ,  MEHTER EBRAHIM ,  RODBELL KENNETH P ,  SCHNABEL FLORIAN ,  WEBER STEFAN J

IPC: H01L23/52 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To limit the forming quantity of an inter-metallic compound by sticking a wetting layer containing first metal which is brought into contact with an insulator to a recessed part, a uniform barrier layer on it, and a second metallic conduction layer on it at a temperature which is lower than that, at which the inter-metal compound is generated by means of diffusing first and second metals on the barrier layer. SOLUTION: Barrier layers 20 of nonreactive compounds are formed on wetting layers 18, where the metal of titanium(Ti) is evaporated by CVD on the sidewalls of the recessed parts 12 of an insulating layer 10 on the substrate 11 of a silicon water. The barrier layers 20 are formed of an arbitrary material, whose diffusion temperature of the constitution elements of the wetting layers 18 and the metallic layers, is higher than the reaction temperature of the constitution elements, and titanium nitride(TiN) is desirable. It is thicker than the sidewalls of the wetting layers 18 and is more uniform. Then, the recessed parts 12 are completely filled with the conduction layers a metal such as aluminum(Al). In the reaction between Ti of the wetting layers 18 and Al of the conduction layers 22, Ti and Al are unable to diffuse at a temperature lower than 430 deg.C, and they are brought into contact with each other and do not react.

公开(公告)号：JP2000049117A

公开(公告)日：2000-02-18

申请号：JP16303399

申请日：1999-06-09

Applicant: IBM ,  SIEMENS AG

Inventor： CLEVENGER LARRY ,  HOINKIS MARK ,  IGGULDEN ROY C ,  WEBER STEFAN J

IPC: H01L21/3205 ,  C23C14/14 ,  C23C14/58 ,  C23C16/56 ,  C23C28/02 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a technology for filling an opening part, such as a trench and barrier of high-aspect ratio using an economical and reliable method. SOLUTION: An improved method for forming a metal filling structure part at an opening part of a substrate 1 of an integrated circuit device is provided. An intermittent metal liner 18 by CVD is formed at an opening part 100, which is to be filled, provided at a dielectrics layer of the substrate 1. On the intermittent metal liner 18, a metal is further deposited by physical vapor-deposition to form a metal filling structure part. Since the intermittent metal liner provides a wettability equal to or better than that of the intermittent (??) CVD liner, an opening part of an opening width significantly narrower than 250 nm can be filled.

公开(公告)号：DE60132435D1

公开(公告)日：2008-03-06

申请号：DE60132435

申请日：2001-03-12

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LARRY ,  HSU LOUIS L ,  NARAYAN CHANDRASEKHAR ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L23/525 ,  H01L21/768

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.

公开(公告)号：DE102004017411B4

公开(公告)日：2010-01-07

申请号：DE102004017411

申请日：2004-04-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  UNITED MICROELECTRONICS CO

Inventor： COWLEY ANDY ,  FANG SUNFEI ,  WANG YUN-YU ,  CLEVENGER LARRY ,  SIMON ANDREW H ,  GRECO STEPHEN ,  CHANDA KAUSHIK ,  SPOONER TERRY ,  YANG CHIH-CHAO

IPC: H01L21/285 ,  H01L21/768

公开(公告)号：DE60132435T2

公开(公告)日：2008-07-31

申请号：DE60132435

申请日：2001-03-12

Applicant: IBM ,  QIMONDA AG

Inventor： CLEVENGER LARRY ,  HSU LOUIS L ,  NARAYAN CHANDRASEKHAR ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L23/525 ,  H01L21/768

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.

公开(公告)号：DE102004017411A1

公开(公告)日：2005-03-10

申请号：DE102004017411

申请日：2004-04-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  UNITED MICROELECTRONICS CO

Inventor： COWLEY ANDY ,  FANG SUNFEI ,  WANG YUN-YU ,  CLEVENGER LARRY ,  SIMON ANDREW H ,  GRECO STEPHEN ,  CHANDA KAUSHIK ,  SPOONER TERRY ,  YANG CHIH-CHAO

IPC: H01L21/768 ,  H01L21/285

公开(公告)号：AU2003298347A1

公开(公告)日：2004-06-30

申请号：AU2003298347

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  TULIPE DOUGLAS JR LA ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.