公开(公告)号：EP2235743A4

公开(公告)日：2013-03-20

申请号：EP09704665

申请日：2009-01-15

Applicant: IBM

Inventor： DALTON TIMOTHY ,  DORIS BRUCE B ,  KIM HO-CHEOL ,  RADENS CARL

IPC: H01L21/033 ,  B81C1/00

CPC classification number: H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：JP2005311366A

公开(公告)日：2005-11-04

申请号：JP2005119003

申请日：2005-04-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  CHIRAS STEFANIE R ,  DALTON TIMOTHY ,  DEMAREST JAMES J ,  DUNN DERREN N ,  DZIOBKOWSKI CHESTER T ,  FLAITZ PHILIP L ,  LANE MICHAEL W ,  LLOYD JAMES R ,  DARYL D RESUTAINO ,  SHAW THOMAS M ,  WANG YUN YU ,  YANG CHIH-CHAO

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To realize an interconnection structure that improves the adhesion between an upper low-k dielectric layer and a diffusion barrier cap dielectric layer existing therebeneath. SOLUTION: In the interconnection structure, adhesion between the upper low-k (for example, the dielectric coefficient is less than 4.0) dielectric layer (for example, a dielectric containing an element group consisting of Si, C, O, and H) and the diffusion barrier cap dielectric layer (for example, a cap layer containing an element group consisting of C, Si, N, and H) existing therebeneath is improved, by providing an adhesion transition layer in between the two layers. Because the adhesion transition layer exists between the upper low-k dielectric layer and the diffusion barrier cap dielectric layer, the possibility that the layers in the interconnection structure are separated in a packaging process is reduced. The adhesion transition layer provided here comprises a lower SiO x (or SiON) contained region and an upper C inclination region. Such a structure and, in particular, a method for forming an adhesion transition layer are also provided. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：实现改善上部低k电介质层和存在于其之间的扩散阻挡盖电介质层之间的粘附性的互连结构。 解决方案：在互连结构中，上部低k（例如，介电系数小于4.0）电介质层（例如，包含由Si，C，O和 H）和扩散阻挡盖电介质层（例如，包含由C，Si，N和H构成的元素组的覆盖层）提高，通过在两层之间提供粘合过渡层。 由于粘附过渡层存在于上部低k电介质层和扩散阻挡层电介质层之间，因此在封装过程中互连结构中的层分离的可能性降低。 这里提供的粘合过渡层包含较低的SiO xS（或SiON）含有区域和上C倾斜区域。 还提供了这种结构，特别是形成粘附过渡层的方法。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：AT503252T

公开(公告)日：2011-04-15

申请号：AT07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL ,  CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  DEBROSSE JOHN ,  HSU LOUIS ,  RADENS CARL ,  WONG KEITH ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

公开(公告)号：DE60332865D1

公开(公告)日：2010-07-15

申请号：DE60332865

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

公开(公告)号：AT470237T

公开(公告)日：2010-06-15

申请号：AT03796085

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：CA2719727C

公开(公告)日：2017-01-03

申请号：CA2719727

申请日：2009-03-30

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  HSU LOUIS ,  RADENS CARL

IPC: H02J50/20 ,  H02J7/00 ,  H02J50/80 ,  H04W88/02

Abstract: A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

公开(公告)号：AT535013T

公开(公告)日：2011-12-15

申请号：AT06740771

申请日：2006-04-07

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE ,  COWLEY ANDREW ,  DALTON TIMOTHY ,  YOON MEEYOUNG

IPC: H01L21/4763 ,  H01L21/768

Abstract: A structure. The structure includes: a core electrical conductor having a top surface, an opposite bottom surface and sides between the top and bottom surfaces; an electrically conductive liner in direct physical contact with and covering the bottom surface and the sides of the core electrical conductor, embedded portions of the electrically conductive liner in direct physical contact with and extending over the core electrical conductor in regions of the core electrical conductor adjacent to both the top surface and the sides of the core electrical conductor; and an electrically conductive cap in direct physical contact with the top surface of the core electrical conductor that is exposed between the embedded portions of the electrically conductive liner.

公开(公告)号：CA2719727A1

公开(公告)日：2009-12-17

申请号：CA2719727

申请日：2009-03-30

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  HSU LOUIS ,  RADENS CARL

IPC: H02J17/00 ,  H02J7/00 ,  H04W88/02

Abstract: A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

公开(公告)号：AT384685T

公开(公告)日：2008-02-15

申请号：AT02803310

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD ,  BISSON JOHN ,  COTE DONNA R ,  DALTON TIMOTHY ,  GROVES ROBERT ,  PETRARCA KEVIN ,  STEIN KENNETH ,  SUBBANNA SESHADRI

IPC: B81C1/00 ,  B81B3/00 ,  H01H49/00 ,  H01H59/00

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.