公开(公告)号：US3285836A

公开(公告)日：1966-11-15

申请号：US29134763

申请日：1963-06-28

Applicant: IBM

Inventor： MAISSEL LEON I ,  STANDLEY CHARLES L

IPC: C25D11/02 ,  C25D11/26 ,  H01L21/00 ,  H01L23/29

CPC classification number: H01L21/00 ,  C25D11/26 ,  H01L23/291 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：US3365378A

公开(公告)日：1968-01-23

申请号：US33485663

申请日：1963-12-31

Applicant: IBM

Inventor： MAISSEL LEON I ,  STANDLEY CHARLES L

IPC: H01G4/06

CPC classification number: H01G4/06

公开(公告)号：US3617463A

公开(公告)日：1971-11-02

申请号：US3617463D

申请日：1969-06-18

Applicant: IBM

Inventor： GREGOR LAWRENCE V ,  MAISSEL LEON I ,  STANDLEY CHARLES L

IPC: C23F4/00 ,  H01J37/30 ,  H01J37/34 ,  H01L21/302 ,  H01L21/3065 ,  H05K3/08 ,  C23C15/00

CPC classification number: H01J37/34

Abstract: The object to be sputter etched is excited in a reduced atmosphere of inert gas by the application of an RF potential across a pair of electrodes, one of which supports the object and is capacitively coupled to the RF source. The improvement is a means to catch and retain material removed by the sputtering operation.

公开(公告)号：CA757606A

公开(公告)日：1967-04-25

申请号：CA757606D

Applicant: IBM

Inventor： STANDLEY CHARLES L ,  MAISSEL LEON I

公开(公告)号：CA1245517A

公开(公告)日：1988-11-29

申请号：CA509373

申请日：1986-05-16

Applicant: IBM

Inventor： BEYER KLAUS D ,  GUTHRIE WILLIAM L ,  MAKAREWICZ STANLEY R ,  MENDEL ERIC ,  PATRICK WILLIAM J ,  PERRY KATHLEEN A ,  PLISKIN WILLIAM A ,  RISEMAN JACOB ,  SCHAIBLE PAUL M ,  STANDLEY CHARLES L

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/306

Abstract: A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier. In a second example a substrate having a paterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.

公开(公告)号：CA1248641A

公开(公告)日：1989-01-10

申请号：CA514222

申请日：1986-07-21

Applicant: IBM

Inventor： CHOW MELANIE M ,  CRONIN JOHN E ,  GUTHRIE WILLIAM L ,  KAANTA CARTER W ,  LUTHER BARBARA J ,  PATRICK WILLIAM J ,  PERRY KATHLEEN A ,  STANDLEY CHARLES L

IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H05K3/04 ,  H05K3/10 ,  H05K3/46 ,  H01L21/72

Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.

公开(公告)号：CA769325A

公开(公告)日：1967-10-10

申请号：CA769325D

Applicant: IBM

Inventor： MAISSEL LEON I ,  STANDLEY CHARLES L

公开(公告)号：CA757284A

公开(公告)日：1967-04-18

申请号：CA757284D

Applicant: IBM

Inventor： STANDLEY CHARLES L ,  MAISSEL LEON I ,  SILCOX NORMAN W