公开(公告)号：CA1159953A

公开(公告)日：1984-01-03

申请号：CA377171

申请日：1981-05-08

Applicant: IBM

Inventor： GARNACHE RICHARD R ,  KENNEY DONALD M ,  THOMA NANDOR G

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78

Abstract: V-MOS Device with Self-Aligned Multiple Electrodes High density VMOSFET devices, particularly single transistor memory cells, are provided by use of series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/ drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode subsequently acts as a self-aligned mask to define implanted source/ drain regions also within the V-groove and to enable second level interconnecting metallurgy contacts to be formed along the sidewalls of the V-groove. BU-978013

公开(公告)号：CA980920A

公开(公告)日：1975-12-30

申请号：CA164187

申请日：1973-02-19

Applicant: IBM

Inventor： RYAN WILLIAM J SR ,  THOMA NANDOR G ,  SCHIRMER EDWARD F ,  TOLLEY JAMES H ,  WILDER DONALD L

IPC: H01L21/00 ,  H01L21/683

Abstract: A system for handling an oriented array of objects, such as integrated circuit chips, includes a fixture in which the chips are held in place by vacuum means. A chip placement tube is capable of reciprocal motion normal to the plane of the fixture to move a chip unidirectionally from its position in the array for placement on a substrate. The system further includes means for positioning a substrate precisely with respect to a chip in the array to allow its direct placement from the array. This fixture and system allows the precise orientation and alignment of semiconductor chips in a wafer to be maintained for laser dicing and chip positioning on a substrate without requiring reorientation. When combined with testing and inspection apparatus and a suitable memory, the system further allows handling and processing of chips to be minimized.

公开(公告)号：DE3371576D1

公开(公告)日：1987-06-19

申请号：DE3371576

申请日：1983-02-01

Applicant: IBM

Inventor： THOMA NANDOR G ,  MOORE VICTOR STEWART ,  KRAFT WAYNE RICHARD

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  H03K19/177

Abstract: The decoding device comprises a plurality of programmable logic arrays (20-24) operating in parallel, each to decode an operation code (OP code) of a given instruction class. A portion of the OP code is decoded by a decode multiplexer (40) to select one of the PLA's, and the decoded OP code from the selected PLA is gated through a N-way multiplexer (42) to provide the control code corresponding to the OP code.

公开(公告)号：CA1199415A

公开(公告)日：1986-01-14

申请号：CA440045

申请日：1983-10-31

Applicant: IBM

Inventor： THOMA NANDOR G ,  MOORE VICTOR S ,  KRAFT WAYNE R

IPC: G06F9/22 ,  G06F9/26

Abstract: MICROWORD GENERATION MECHANISM UTILIZING A SEPARATE BRANCH DECISION PROGRAMMABLE LOGIC ARRAY A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes programmable logic array means responsive to the processor instructions for producing the appropriate microword sequences. The microword generation mechanism also includes condition indicator circuitry for supplying indicator signals indicating whether the results of arithmetic and logic operations in the processor meet certain types of conditions. The microword generation mechanism further includes a condition testing programmable logic array responsive to the condition field of a conditional branch type processor instruction for testing the appropriate indicator signal or signals and causing a branch type microword sequence to be produced if the specified condition is met.

公开(公告)号：CA1180456A

公开(公告)日：1985-01-02

申请号：CA417165

申请日：1982-12-07

Applicant: IBM

Inventor： WYATT VIRGIL D ,  KRAFT WAYNE R ,  THOMA NANDOR G

IPC: G06F7/00 ,  G06F9/30 ,  G06F13/40 ,  G06F15/78 ,  H01L23/52

Abstract: LARGE SCALE INTEGRATION DATA PROCESSOR SIGNAL TRANSFER MECHANISM A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus. The signal transfer mechanism further includes processor control circuitry coupled to the signal source and signal destination circuitry for enabling the signal source circuitry to put a plural-bit data signal onto the data bus during a first processor control cycle and for enabling the signal destination circuitry to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.