公开(公告)号：JPH10301794A

公开(公告)日：1998-11-13

申请号：JP8516798

申请日：1998-03-31

Applicant: IBM

Inventor： KENNETH J GOODNOW ,  CLARENCE R OGIRUBII ,  WILBUR D PRISER ,  SABASTIAN T VENTOLON

IPC: G06F9/46 ,  G06F12/08 ,  H04M3/00

Abstract: PROBLEM TO BE SOLVED: To prevent the stoppage of a processor by task changeover by predicting the next task to be processed and loading the next task to a cache memory before the execution of the task. SOLUTION: This information processing system is provided with at least one processor, that is a central processing unit(CPU) 10, the cache memory 13 provided in the CPU 10 is provided with the storage hierarchy of a single level or plural levels and the CPU 10 is provided with a task queue 42 further. The task queue 42 is provided with plural task registers 44, 46,...52 and the task registers store a task list in a time-based processing order from the present task to the next task. By using the task list, before the CPU 10 completes the processing of the present task, the point of time of loading the next task to the cache memory 13 is predicted. Also, by allocating a task ID to the respective tasks, the task is identified.

公开(公告)号：JP2000101093A

公开(公告)日：2000-04-07

申请号：JP24211799

申请日：1999-08-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  EDWARD J NOWACK ,  WILBUR D PRISER ,  MIN H TONG

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a device structure of SOI(silicon on isulator) CMOS (complementary metal oxide semiconductor) in which avalanche multiplication of current flowing through a device is increased when an FET(field effect transistor) is turned on and body charges are removed when the FET is turned off. SOLUTION: An FET having an electric floating body is substantially isolated electrically from a substrate. A high resistance path 16 for coupling the floating body is provided at the source. The resistor is operated as a floating body for active switching and a body grounded in waiting mode in order to reduce leakage current. The high resistance path has a resistance of at least 1 MΩ and made of polysilicon. The resistor is formed using a split polysilicon process for opening a hole in a first polysilicon layer in order that an embedded contact mask 19 brings a second polysilicon layer into contact with the substrate.

公开(公告)号：JP2001313372A

公开(公告)日：2001-11-09

申请号：JP2001090567

申请日：2001-03-27

Applicant: IBM

Inventor： JENNIFER D LYNCH ,  WILBUR D PRISER ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/70 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/02 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable chip-on-capacitor. SOLUTION: The capacitor (94) in a semiconductor device (20) has a lower copper plate (30) in a damascene/trench (22), barrier layers (56, 180a) disposed above the lower plate, a dielectric layer (60) disposed above the barrier layers and an upper plate (96) above the dielectric layer. Another embodiment of this invention is capacitors (296, 396) in a semiconductor device, which has two lower plates (230, 231, 330, 331) mutually separated, dielectric layers (260, 360) above the lower plate and upper plates (296, 396) above the dielectric layer which covers the lower plate, extends preferably across it. This invention further includes a method for manufacturing the capacitor of such a constitution.

公开(公告)号：JP2000200490A

公开(公告)日：2000-07-18

申请号：JP36405499

申请日：1999-12-22

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  WILBUR D PRISER

IPC: G11C11/412 ,  H01L21/8244 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To obtain a CMOS-SRAM having a reduced total number of transistors and a corresponding reduced surface region. SOLUTION: This cell has a pair of P channel transistor 22, 23 and a pair of N channel transistor 26, 27 connected as a bistable latch. A first common source connection part is connected to a write-in bit terminal, a residual source connection part is connected to a complementary bit line. A work line is given to a transistor connected to a bit line having contacts 22, 23 permitting read-out and write-in for a latch. At the time of a write-in mode, a work line is connected to a potential at which a transistor connected to a bit line is conducted, a write-in bit is connected to a potential at which residual transistors are made non-conductive. At the time of read operation, one of residual transistors is made to conduct and a work line conducts a pair of transistors connected to a bit line.