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公开(公告)号：JP2003198274A
公开(公告)日：2003-07-11
申请号：JP2002234488
申请日：2002-08-12
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , BETTI GIORGIO , CHRAPPAN SOLDAVINI FRANCESCO , HASSNER MARTIN AURELIANO
Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a nonlinear passive element. SOLUTION: The circuit refers to nonlinear electronic equipment, especially in a nonlinear capacitor, more specifically, to the electronic circuit device that can be integrated on a semiconductor substrate (not limited). A nonlinear device is advantageously set to be a capacitor consisting of the feedback loop of a plurality of active blocks (2, 5, and 6), that are mutually subjected to cascade connection. Further, the invention can be integrated with or can be used relating to a network including other pieces of nonlinear device. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2003142988A
公开(公告)日：2003-05-16
申请号：JP2002234482
申请日：2002-08-12
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , BETTI GIORGIO , CHRAPPAN SOLDAVINI FRANCESCO , HASSNER MARTIN AURELIANO
IPC: H01L21/822 , H01L27/04 , H03H11/48
Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a non-linear passive element. SOLUTION: The invention relates to a non-linear electronic device and, more particularly, to a non-linear inductor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a inductor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.
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公开(公告)号：JPH0855436A
公开(公告)日：1996-02-27
申请号：JP32378294
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： GADDUCCI PAOLO , MOLONEY DAVID , BETTI GIORGIO
Abstract: PURPOSE: To provide a survival sequence register of a simple structure having high reliability, by receiving a stream of logical sum of serial input streams SWP and SWN from G1, causing a first shift register F7 -F14 to remove spurious components, and causing a control circuit to generate an erase signal. CONSTITUTION: A survival sequence register is supplied with inputs of coded digital signals SWP, SWN corresponding to positive/negative certification peaks from a pickup and a clock signal CLK, and includes a variable threshold qualification circuit. The survival sequence register receives a logical sum output of SWP, SWN from an OR circuit G1 and removes spurious components by a shift register made of flip-flops F7 -F14 . A control circuit generates an erase signal. A second pointer shift register shifts through F7 -F14 and points out logic '1' of a sequence preceding logic '1' corresponding to a detection peak of the same code corresponding to the preceding logic '1'. With this structure, an SSR for variable threshold certification for channel recording having a simple structure and high reliability may be provided.
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公开(公告)号：JPH07176138A
公开(公告)日：1995-07-14
申请号：JP25471694
申请日：1994-09-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , BETTI GIORGIO , ALINI ROBERTO
Abstract: PURPOSE: To prevent the generation of errors by the transmission delay of signals by storing bits finally processed in a second combinational logic network (RC1) in a shift register, predicting the time when (n) bits are process in a first RC1 and synthesizing the signals in a second RC2. CONSTITUTION: The first RC1 processes the Q output tap (6:0) value of an FF for forming the shift register SR prior to the processing by the second RC2 of the corresponding bit for the complete two cycles of a synchronous block signal VCO. In order to secure the utilization of the entire cycle of the clock signal VCO which is a corresponding decoding value ND1 in the input D of the output register (FF) of a decoding NRZ output stream, a frequency which is partial compared to the base synchronous clock signal VCO in front of the rising front of a first clock signal and matched with the bit number ratio of input and output streams is provided. The bit finally processed in the RC2 is tentatively stored in the shift registers Q1-Q7, the time when the (n) bits are processed in the RC1 is predicted and the signals are synthesized in the RC2.
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公开(公告)号：JPH07115355A
公开(公告)日：1995-05-02
申请号：JP24706894
申请日：1994-09-14
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , GADDUCCI PAOLO , MOLONEY DAVID
IPC: H03F1/30 , H03F3/45 , H03K5/1536 , H03K17/13 , H03K17/60
Abstract: PURPOSE: To eliminate the equivalent input offset of a comparator stage by cyclically inverting the connection of the input terminal of a comparator for supplying input signals after a detected zero cross. CONSTITUTION: After detecting that the zero cross is generated, comparison is performed with a minimum interval between the optional continuous two times of the zero crosses of the input signals S1 and an output state taken by the comparator G1 for practically small preliminarily set time is stored. This circuit is realized by using a deviater D for switching the input connection of the comparator G1 for supplying output signals S2 to the clock input terminal CK of a flip-flop for storing the output state. The flip-flop is sensitive to the unidirectional transition of clock signals S2 and the deviater D is driven by signals S7 delayed for a preliminarily set time interval by a delay circuit.
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Patent Agency Ranking
公开(公告)号：JP2001274657A
公开(公告)日：2001-10-05
申请号：JP2001031150
申请日：2001-02-07
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ROSSI AUGUSTO , BETTI GIORGIO , CAZZANIGA MARCO
Abstract: PROBLEM TO BE SOLVED: To provide an FIR filter design that has a structure and a functional feature suitable for processing a signal whose spectrum is not known in advance and executes Hilbert transform so as to eliminate limitations and overcome defects of the design of a conventional technology. SOLUTION: This invention relates to a time continuous FIR(finite impulse response) filter that executes the Hilbert transform. The filter is provided with a delay cell connected in cascade between an input terminal and an output terminal of the filter and with a programmable time delay(Td) for a programmable filter cell having fixed filter coefficients (c0,..., cn). Furthermore, this invention also relates to a filtering method to use the structure of the Hilbert FIR filter to process a signal produced by reading data from a magnetic storage medium adopting the vertical recording.
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公开(公告)号：JPH06326536A
公开(公告)日：1994-11-25
申请号：JP9365394
申请日：1994-04-06
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , MOLONEY DAVID , PORTALURI SALVATORE
Abstract: PURPOSE: To provide a variable gain amplifier provided with high dynamic characteristics and a wide frequency band, operated by a low voltage combining output signals which are generated by first and second amplifiers and a variable current oscillator and converting them by a converter. CONSTITUTION: This variable gain amplifier VGA is composed of a first voltage- current (V/I) amplifier, provided with a fixed gain and a second V/I amplifier provided with a variable gain operated in parallel with a first amplifier. Then, the output currents of the first and second amplifiers are totaled in a circuit for totaling and third current signals generated by the variable current oscillator driven by a control voltage VCONTROL are totaled as well. Then, the circuit Σfor totaling is used among three circuit blocks and a current-voltage converter (I/V) and supplies a low impedance node for totaling the output currents. Thus, the I/V converter converts the total of the output current signals of the three blocks into voltage signals.
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公开(公告)号：JPH04239218A
公开(公告)日：1992-08-27
申请号：JP15065091
申请日：1991-06-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948
Abstract: PURPOSE: To provide a tri-state output gate structure capable of reducing active inputs and removing or substantially reducing the series connection of plural P-channel transistors(TRs) and allowed to be easily integrated by a CMOS integrated circuit. CONSTITUTION: The structure includes an active terminal 30 for receiving an active signal and an input terminal 31 for receiving an input signal and the input terminal 31 connects an output terminal 32 to a positive power supply terminal or a negative power supply terminal through a signal switching means 38. The active terminal 30 can be electrically connected to the gate terminal of a 1st P-channel TR 33 and the gate terminal of a 2nd N-channel TR 34 through signal inversion means 35, 37. The output terminal 32 is electrically connected to the drain terminals of the 1st and 2nd TRs 33, 34. The 1st and 2nd TRs 33, 34 electrically insulate the output terminal 32 from the input terminal 31.
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公开(公告)号：JPH03220913A
公开(公告)日：1991-09-30
申请号：JP30281290
申请日：1990-11-09
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/2897 , H03K3/0233
Abstract: PURPOSE: To reduce dependency against the inclination of the input signal waveform of an output change by providing a second differential cell having one input connected to output and the other input connected to a control circuit part provided with respective outputs connected to threshold input. CONSTITUTION: A transistor T9 is provided with a base B9 which is directly connected to an output terminal OUT as input for a second differential cell 9 and a collector C9 connected to a power electrode Vc. In the other transistor T10, the base B10 is connected to ground via a current power as second input and is connected to the emitter E11 of an npn-type transistor T14. T14 is connected to become diode constitution in the device 1, and the collector C14 is directly connected to the emitter E15 of the transistor T15. Threshold input S is connected to the collector C10 of the transistor T10 in the cell 9 and a comparator 1 is provided with the circuit part 10 effective for controlling a voltage value Vs appearing on threshold input S. Thus, dependency against the inclination of the input signal waveform of the output change can be reduced.
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公开(公告)号：EP0427016B1
公开(公告)日：1997-12-29
申请号：EP90119873
申请日：1990-10-17
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/2897 , H03K3/0233 , H03K3/023
CPC classification number: H03K3/02337
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