中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.024 seconds)

    SYNCHRONOUS READING NONVOLATILE MEMORY
    1.
    发明专利
    SYNCHRONOUS READING NONVOLATILE MEMORY 审中-公开

    公开(公告)号：JP2002230986A

    公开(公告)日：2002-08-16

    申请号：JP2002006161

    申请日：2002-01-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRULIO MASSIMILIANO ,  VILLA CORRADO ,  BARTOLI SIMONE

    IPC: G11C16/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32

    Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile memory which can perform synchronous reading with a frequency higher than a frequency which can be used now for data stored in a nonvolatile memory and which is operated by a burst reading mode. SOLUTION: This nonvolatile memory (10) is provided with an input pin (2) receiving an external clock signal supplied by a user, an input buffer (4) receiving the external clock signal and supplying an intermediate clock signal relating to the external clock signal and being delayed, and a delayed lock loop (12) receiving the intermediate clock signal and supplying the intermediate clock signal distributed in the nonvolatile memory and synchronizing with the external clock signal substantially.

    FLASH EEPROM MEMORY ARRAY AND BIASING METHOD THEREFOR
    3.
    发明专利
    FLASH EEPROM MEMORY ARRAY AND BIASING METHOD THEREFOR 失效

    公开(公告)号：JPH0855921A

    公开(公告)日：1996-02-27

    申请号：JP9322995

    申请日：1995-03-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DALLABORA MARCO ,  SALI MAURO LUIGI ,  TASSAN CASER FABIO ,  VILLA CORRADO

    IPC: H01L21/8247 ,  G11C16/04 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PURPOSE: To provide a NOR flash type memory array corresponding to the programming of small current without changing any auxiliary element such a decode, sense and load devices. CONSTITUTION: Concerning a flash EEPROM memory array 35, asymmetric structure is provided by memory cells 36 having source areas composed of row/column style and connected to respective bit lines BL, source regions connected to common source lines BLS and control gate regions connected to respective work lines WL and in that asymmetric structure, either the source region or the drain region provides a high resistant section so that the cells in various areas can be programmed and erased. The memory array 35 includes a bias transistor 41 for preventing spurious writing by keeping the drain region and source region of cell connected to the bit line, to which any address is not designated, at the same potential when programming.

    Supply voltages switch circuit
    4.
    发明公开
    Supply voltages switch circuit 失效
    电路的工作电压

    公开(公告)号：EP0782268A3

    公开(公告)日：1998-11-04

    申请号：EP96830353

    申请日：1996-06-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  BETTINI LUIGI ,  BARTOLI SIMONE

    IPC: G11C5/14 ,  G11C16/12 ,  H03K17/687 ,  H03K17/693

    CPC classification number: G11C5/143 ,  G11C16/12 ,  H03K17/6871 ,  H03K17/693

    Abstract: A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors (MA,MB;Mc,MD) connected in series provides that at least one branch (2) of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first (5) and a second (4) pairs of transistors (M1,M2,M3,M4) connected between a first supply voltage reference (SUPPLY1) and a common node (D). The first pair (5) comprises transistors (M1,M2) bigger than the transistors (M3,M4) of the second pair (4) while between the transistors (M3,M4) making up the second pair (4) is inserted a pair of resistors (R1,R2). Between the pair of resistors (R1,R2) there is an interconnection node (F) connected to a corresponding interconnection node (E) between the transistors (M1,M2) of the first pair (5).

    7.
    发明专利
    未知

    公开(公告)号：DE69516883T2

    公开(公告)日：2000-10-05

    申请号：DE69516883

    申请日：1995-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  DEFENDI MARCO ,  BETTINI LUIGI

    IPC: G11C16/16 ,  G11C11/00

    Abstract: The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

    8.
    发明专利
    未知

    公开(公告)号：DE69516883D1

    公开(公告)日：2000-06-15

    申请号：DE69516883

    申请日：1995-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  DEFENDI MARCO ,  BETTINI LUIGI

    IPC: G11C16/16 ,  G11C11/00

    Abstract: The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

    9.
    发明专利
    未知

    公开(公告)号：DE60329899D1

    公开(公告)日：2009-12-17

    申请号：DE60329899

    申请日：2003-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIMERCATI DANIELE ,  SCHIPPERS STEFAN ,  MIRICHIGNI GRAZIANO ,  VILLA CORRADO

    IPC: G11C16/08 ,  G11C8/08

    Abstract: A circuit (300) is proposed for driving a memory line (110) controlling at least one memory cell (105) of a non-volatile memory device (100), the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter (120s) for converting the first selection signal into a first operative signal and a second level shifter (120g) for converting the second selection signal into a second operative signal, each level shifter including first shifting means (210s, 210g) for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector (140) for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means (305s, 305g) for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

Patent Agency Ranking