公开(公告)号：EP1324344A1

公开(公告)日：2003-07-02

申请号：EP02019284.5

申请日：2002-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Emanuele

IPC: G11C11/56 ,  G11C7/06 ,  G11C16/28

CPC classification number: G11C11/5621 ,  G11C7/06 ,  G11C7/062 ,  G11C11/56 ,  G11C11/5642 ,  G11C2207/063

Abstract: The invention relates to a sense amplifier structure (5) for multi-level non-volatile memories, as well as to a method of reading the contents of the memory cells. In particular, a current (Ic) drawn by a memory cell to be read is compared to a current (Irif) drawn by a reference cell through a sense amplifier (2) that has one input terminal (I1) connected to a circuit node to which said currents are led. Advantageously, the currents are compared at both inputs of the sense amplifier (2) by connecting a second input (I2) of said amplifier (2) to a circuit node to which said currents are led, with opposite signs.
The invention enhances the read precision of the sense amplifier for a given data acquisition time by doubling the differential input voltage.

Abstract translation: 本发明涉及用于多级非易失性存储器的读出放大器结构（5）以及读取存储器单元的内容的方法。 特别地，将要读取的存储单元绘制的电流（Ic）与由参考单元通过读出放大器（2）绘制的电流（Irif）进行比较，读出放大器（2）具有连接到电路节点的一个输入端（I1） 这说明了电流被引导。 有利地，通过将​​所述放大器（2）的第二输入（I2）连接到所述电流被引导到的电路节点上，以相反的符号比较在读出放大器（2）的两个输入处的电流。 本发明通过将差分输入电压加倍来提高读出放大器对给定数据采集时间的读取精度。

公开(公告)号：EP1237279A1

公开(公告)日：2002-09-04

申请号：EP01830113.5

申请日：2001-02-21

Applicant: STMicroelectronics S.r.l.

Inventor： Bedarida, Lorenzo ,  Confalonieri, Emanuele ,  Corradi, Andrea ,  Fiorina, Sara

IPC: H03K19/003 ,  H03K19/094

CPC classification number: H03K19/00384

Abstract: Output buffer in which the switching speed of the transistors (4,5) of the output stage (1) is kept constant, independently of the variations of the supply voltage (Vcc) and of the temperature, within the acceptable operating range for the device, by controlling, as a function of the supply voltage and the operating temperature detected by a correction circuit (14), the conductivity of additional transistors (13,15) in series with the transistors (7,8) of the predriving stage (2) which drive the transistors of the output stage in conduction, the transistors being driven by an analog signal (CNTRN, CNTRP) which is generated by the correction circuit (14) and is variable with the supply voltage and the operating temperature.

Abstract translation: 输出缓冲器，其中所述输出级（1）的晶体管（4,5）的开关速度保持恒定，电源电压（Vcc）的变化的unabhängig和温度的，在可接受的工作范围为在该装置内 通过控制，作为电源电压的函数，并且通过校正电路（14）检测到的工作温度，附加晶体管（13,15）串联在预驱动级的晶体管（7,8）的电导率（2 ）你推动传导所述输出级的晶体管，该晶体管由在由所述校正电路（14）产生的，并与电源电压和工作温度变量的模拟信号（CNTRN，CNTRP）所有驱动。

公开(公告)号：EP1418589A1

公开(公告)日：2004-05-12

申请号：EP02425676.0

申请日：2002-11-06

Applicant: STMicroelectronics S.r.l.

Inventor： Lisi, Carlo ,  Ferrario, Marco ,  Scotti, Massimiliano ,  Confalonieri, Emanuele

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/04

Abstract: Described herein is a device (20) for timing random reading of a memory device with a data access time (T A ), in which reading is performed by means of a succession of consecutive operations, the timing device (20) being designed to generate, for each operation, a corresponding timing signal (PS(i)) such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration (T F (i)), which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration (T F (i)); the sum of the fixed durations (T F (i)) being equal to the data access time (T A ) of the memory device.

Abstract translation: 这里描述了一种用于定时随机读取具有数据访问时间（TA）的存储器件的装置（20），其中通过一系列连续操作进行读取，所述定时装置（20）被设计成生成 对于每个操作，相应的定时信号（PS（i）），使得无论存储器件的操作条件如何，相应的操作持续相当于相应的固定持续时间（TF（i））的时间，哪个 被确定为保证在固定持续时间（TF（i））内存储器件的最差工作状态下的操作完成; 固定持续时间（TF（i））的总和等于存储器件的数据访问时间（TA）。

公开(公告)号：EP1400980A1

公开(公告)日：2004-03-24

申请号：EP02425562.2

申请日：2002-09-17

Applicant: STMicroelectronics S.r.l.

Inventor： Poidomani, Carla ,  Confalonieri, Emanuele ,  Sforzin, Marco ,  Del Gatto, Nicola

IPC: G11C16/24 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C16/24

Abstract: A circuit (125,130) for biasing an input node (Na) of a sense amplifier (115) is proposed. The circuit includes means (125) for keeping the input node at a pre-set operative voltage during a sensing operation; the circuit of the invention further includes means (250) for pulling the input node from a starting voltage towards a power supply voltage (+Vdd), the operative voltage being comprised between the starting voltage and the power supply voltage, and control means (255) for disabling the means for pulling before the input node reaches the operative voltage.

Abstract translation: 一种用于在读出放大器（115）的输入节点（Na）的偏压电路（125.130）的提议。 该电路包括用于在传感操作保持在预先设定的工作电压的输入节点的装置（125）; 本发明的电路进一步包括：用于从一个起动电压向电源电压（+ VDD），工作电压被包括起始电压和电源电压，和控制装置之间拉动所述输入节点装置（250）（255 ），用于禁止所述用于拉动输入节点达到工作电压之前。

公开(公告)号：EP1670002B8

公开(公告)日：2008-02-27

申请号：EP05025286.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cascone, Davide ,  Del Gatto, Nicola ,  Confalonieri, Emanuele ,  Mollichelli, Massimiliano

IPC: G11C16/30

CPC classification number: G11C16/30

公开(公告)号：EP1670002B1

公开(公告)日：2007-10-03

申请号：EP05025286.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cascone, Davide ,  Del Gatto, Nicola ,  Confalonieri, Emanuele , 

IPC: G11C16/30

CPC classification number: G11C16/30

公开(公告)号：EP1686591B1

公开(公告)日：2008-01-09

申请号：EP05100551.0

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Ferrario, Marco ,  Confalonieri, Emanuele

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26

公开(公告)号：EP1324344B1

公开(公告)日：2007-04-04

申请号：EP02019284.5

申请日：2002-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Emanuele

IPC: G11C11/56 ,  G11C7/06 ,  G11C16/28

CPC classification number: G11C11/5621 ,  G11C7/06 ,  G11C7/062 ,  G11C11/56 ,  G11C11/5642 ,  G11C2207/063

公开(公告)号：EP1670002A1

公开(公告)日：2006-06-14

申请号：EP05025286.5

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Cascone, Davide ,  Del Gatto, Nicola ,  Confalonieri, Emanuele ,  Mollichelli, Massimiliano

IPC: G11C16/30

CPC classification number: G11C16/30

Abstract: A method for configuring a voltage regulator (20) connected to a memory cell (1) is described, the method comprising the steps of:

identifying at least a first and a second operation regions of the cell (1);
associating the first and second operation regions with respective first and second operation conditions of the cell (1);
detecting an operative condition of the cell (1) involved in a programming operation;
generating at least a configuration signal (EN_LOW_IPROG_HV) of the regulator according to said detected operative condition, this configuration signal (EN_LOW_IPROG_HV) taking a first and a second value associated with the first and second operation conditions.

Abstract translation: 描述了一种用于配置连接到存储单元（1）的电压调节器（20）的方法，该方法包括以下步骤：识别单元（1）的至少第一和第二操作区域; 将所述第一和第二操作区域与所述单元（1）的各自的第一和第二操作条件相关联; 检测参与编程操作的单元（1）的操作状态; 根据所述检测到的操作条件至少产生调节器的配置信号（EN_LOW_IPROG_HV），该配置信号（EN_LOW_IPROG_HV）取第一和第二值与第一和第二操作条件相关联。

公开(公告)号：EP1830468A1

公开(公告)日：2007-09-05

申请号：EP06425144.0

申请日：2006-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Versari, Roberto ,  Mollichelli, Massimiliano ,  Del Gatto, Nicola ,  Rosito, Nicola ,  Confalonieri, Emanuele

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M1/785

Abstract: A description has been given of a regulator for a digital-to-analog converter having in input a digital signal (BUS ) and being suitable for providing an analog signal (Vout) in output. The regulator comprises at least one pair of buffers (Buf1, Buf2..Bufn) having in input said digital signal (BUS ) and the outputs connected to a pair of circuit branches (r1, r2..rn) connected to the output of the regulator; each of said at least two circuit branches comprises at least one resistance. To at least one (Buf2, Buf3...Bufn)) of said at least one pair of buffers a variable resistance (Rv2...Rvn) is associated and the regulator comprises means (10) having in input the analog signal and being suitable for measuring its trend and acting on the variable resistance (Rv2...Rvn) in response to its possible anomalous trend compared to a desired trend.

Abstract translation: 已经给出了一种用于数模转换器的稳压器的描述，该数模转换器具有输入数字信号（BUS i）并且适于在输出中提供模拟信号（Vout）。 调节器包括至少一对缓冲器（Buf1，Buf2..Bufn），其中输入了所述数字信号（BUSI），并且输出端连接到一对电路分支（r1，r2..rn） 调节器输出; 所述至少两个电路分支中的每一个包括至少一个电阻。 对于所述至少一对缓冲器中的至少一个（Buf2，Buf3 ... Bufn），可变电阻（Rv2 ... Rvn）相关联，并且调节器包括在输入模拟信号并且为 适合于测量其趋势并作用于可变电阻（Rv2 ... Rvn），以响应与期望趋势相比可能的异常趋势。