公开(公告)号：EP2299481A2

公开(公告)日：2011-03-23

申请号：EP10015719.7

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
- forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
- forming in the first semiconductor layer (21) first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
- forming in the first semiconductor layer (21) second sub-regions (D1, D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
- forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
- carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 用于制造集成在其上形成漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏功率电子器件（30）的工艺，其特征在于其包括以下步骤： - 在 在所述半导体衬底（100）上形成漏极外延层（20）的第一电阻率值（ρ1）的第一导电类型的第一半导体外延层（21）， - 在所述第一半导体层（21） 借助于具有第一注入剂量（Φ1P）的第一选择性注入步骤的第二导电类型的第一子区域（51）;在第一半导体层（21）中形成第二导电类型的第二子区域（D1，D1a） 借助于具有第二注入剂量（Φ1N）的第二注入步骤的第一导电类型， - 形成表面半导体层（23），其中形成第二导电类型的本体区域（40）与第一子区域 - 区域（51）， - carryin 形成热扩散工艺，使得第一子区域（51）形成与主体区域（40）对准并电接触的单个电连续柱状区域（50）。

公开(公告)号：EP1258927B1

公开(公告)日：2005-08-17

申请号：EP01830308.1

申请日：2001-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Coffa, Salvatore ,  Libertino, Sebania ,  Frisina, Ferruccio

IPC: H01L31/107 ,  H01L31/0288

CPC classification number: H01L31/107 ,  H01L31/0288 ,  Y02B10/10 ,  Y02E10/50

公开(公告)号：EP0693773B1

公开(公告)日：2005-02-09

申请号：EP94830355.7

申请日：1994-07-14

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Ferla, Giuseppe ,  Frisina, Ferruccio

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/74

CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high-speed MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a lightly doped semiconductor layer (1) of a first conductivity type, the elementary functional units comprising channel regions (6) of a second conductivity type covered by a conductive insulated gate layer (8) comprising a polysilicon layer (5); the conductive insulated gate layer (8) also comprises a highly conductive layer (9) superimposed over said polysilicon (5) layer and having a resistivity much lower than the resistivity of the polysilicon layer (5), so that a resistance introduced by the polysilicon layer (5) is shunted with a resistance introduced by said highly conductive layer (9) and the overall resistivity of the conductive insulated gate (8) layer is lowered.

公开(公告)号：EP1310993A2

公开(公告)日：2003-05-14

申请号：EP02024185.7

申请日：2002-10-30

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Magri', Angelo ,  Pinto, Antonio

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/10 ,  H01L23/485 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L29/41741 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: The invention relates to an electronic power device (1) of improved structure and fabricated with MOS technology to have at least one gate finger region (3) and corresponding source regions (4) on opposite sides of the gate region (3). This device (1) has at least one first-level metal layer (3',4') arranged to independently contact the gate region (3) and source regions, and has a protective passivation layer (5) arranged to cover the gate region (3). Advantageously, a wettable metal layer (7), deposited onto the passivation layer (5) and the first-level metal layer (4'), overlies said source regions (4). In this way, the additional wettable metal layer (7) is made to act as a second-level metal.

Abstract translation: 本发明涉及一种在改进的结构（1）的功率电子装置和MOS技术制造成具有至少一个栅极指区域（3）和相应的源极区（4）在所述栅极区的相对侧（3）。 （1）具有至少一个第一级金属层（3”，4' ）设置在该装置unabhängig接触栅极区域（3）和源极区，以及具有布置以覆盖所述栅极区的保护钝化层（5） （3）。 有利的是，沉积在钝化层（5）和所述第一级金属层（4“）的可湿性金属层（7）覆盖所述源极区域（4）。 以这种方式，附加的润湿性的金属层（7）由以作为第二级金属。

公开(公告)号：EP0696054B1

公开(公告)日：2002-02-20

申请号：EP94830331.8

申请日：1994-07-04

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Ferla, Giuseppe ,  Frisina, Ferruccio

IPC: H01L21/336

CPC classification number: H01L29/66719 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  Y10S148/126

公开(公告)号：EP0689238B1

公开(公告)日：2002-02-20

申请号：EP94830315.1

申请日：1994-06-23

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Ferla, Giuseppe ,  Frisina, Ferruccio

IPC: H01L21/336

CPC classification number: H01L29/66712 ,  H01L29/1095

公开(公告)号：EP1160873A1

公开(公告)日：2001-12-05

申请号：EP00830360.4

申请日：2000-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Frisina, Ferruccio ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634

Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and apart (1) of said power device which is placed between zones where the elementary active units are formed. The part (1) of the power device comprises at least two heavily doped body regions (4) of a first conductivity type which are formed in a semiconductor layer (3) of a second conductivity type, a first lightly doped semiconductor region (5) of the first conductivity type which is placed laterally between the two body regions (4). The first semiconductor region (5) is placed under a succession of a thick silicon oxide layer (9), a polysilicon layer (10) and a metal layer (13). A plurality of second lightly doped semiconductor regions (6) of the first conductivity type are placed under said at least two heavily doped body regions (4) and under said first lightly doped semiconductor region (5) of the first conductivity type, each region (6) of said plurality of second lightly doped semiconductor regions (6) of the first conductivity type being separated from the other by portions of said semiconductor layer (3) of the second conductivity type.

Abstract translation: 描述了一种MOS技术功率器件，其包括多个基本有源单元，并且分离（1）所述功率器件，放置在形成基本有源单元的区域之间。 功率器件的部分（1）包括形成在第二导电类型的半导体层（3）中的至少两个第一导电类型的重掺杂体区域（4），第一轻掺杂半导体区域（5） 的横向放置在两个主体区域（4）之间的第一导电类型。 第一半导体区域（5）被放置在厚氧化硅层（9），多晶硅层（10）和金属层（13）的一连串之下。 第一导电类型的多个第二轻掺杂半导体区域（6）放置在所述至少两个重掺杂体区域（4）的下方，并且位于第一导电类型的所述第一轻掺杂半导体区域（5）的下方，每个区域 所述第一导电类型的所述多个第二轻掺杂半导体区域（6）的所述第二导电类型的所述半导体层（3）的一部分与所述第二导电类型的所述多个第二轻掺杂半导体区域（6）分离。

公开(公告)号：EP2259327A3

公开(公告)日：2011-06-29

申请号：EP10180038.1

申请日：2002-11-14

Applicant: STMicroelectronics S.r.l.

Inventor： Magrì, Angelo ,  Frisina, Ferruccio

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/265 ,  H01L29/872

CPC classification number: H01L29/66719 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/872

Abstract: An insulated gate planar power device with a Schottky diode in parallel thereto, said Schottky diode being realized by contacting with a metal layer a semiconductor substrate of a first type of conductivity and the contact zone being laterally surrounded by one or more diffused regions of opposite type of conductivity formed in said substrate for shielding the electric field under conditions of reverse bias of the diode, characterized in that it comprises, in said semiconducting substrate, a buried region doped with a dopant of opposite type of conductivity to that of said semiconductor substrate, geometrically located under said Schottky contact zone and at a greater depth than the depth of said diffused regions.
A relative process of fabrication is also disclosed.

公开(公告)号：EP0961325B1

公开(公告)日：2008-05-07

申请号：EP98830321.0

申请日：1998-05-26

Applicant: STMicroelectronics S.r.l.

Inventor： Magri' Angelo ,  Frisina, Ferruccio

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7802

Abstract: High density MOS technology power device structure, comprising body regions (31A-31D) of a first conductivity type formed in a semiconductor layer (1) of a second conductivity type, characterized in that said body regions comprise at least one plurality of substantially rectilinear and substantially parallel body stripes (32) each joined at its ends to adjacent body stripes (32) by means of junction regions (33), so that said at least one plurality of body stripes (32) and said junction regions (33) form a continuous, serpentine-shaped body region (31A-31D).

公开(公告)号：EP1742259A1

公开(公告)日：2007-01-10

申请号：EP05425494.1

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
- forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
- forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
- forming second sub-regions (D1,D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
- forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
- carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 一种集成在形成漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏极功率电子器件（30）的制造方法，其特征在于包括以下步骤： 至少形成在所述半导体衬底（100）上形成所述漏极外延层（20）的电阻率（α）的第一值的第一类型的导电性的第一半导体外延层（21）， - 形成所述第一子区域（51） 通过具有第一注入剂量（| 1P）的第一选择性注入步骤，通过第二种注入步骤形成第一类型导电性的第二子区域（D1，D1a） 第二植入剂量（| 1N）， - 形成表面半导体层（23），其中形成第二导电类型的体区（40）与第一子区（51）对准， - 执行热扩散过程 使得第一子区域（51）fo rm是单个电连续柱区域（50），其对准并与身体区域（40）电接触。