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    Programming method for a multilevel memory cell
    3.
    发明公开
    Programming method for a multilevel memory cell 有权
    Programmierverfahrenfüreine Mehrpegelspeicherzelle

    公开(公告)号：EP1215679A1

    公开(公告)日：2002-06-19

    申请号：EP01129768.6

    申请日：2001-12-13

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Sandre, Guido ,  Pasotti, Marco ,  Rolandi, Pier Luigi ,  Guaitini, Giovani ,  Iezzi, David ,  Poles, Marco

    IPC: G11C11/56

    CPC classification number: G11C11/5635 ,  G11C11/5621 ,  G11C11/5628 ,  G11C17/146

    Abstract: The invention relates to a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), which method comprises the phases of:

    initially programming (I) a cell threshold value (VthDATI) to a first set of levels [O;(m-1)] being (m) a submultiple of the plurality (N) of levels of the multilevel cell;
    reprogramming without erasing (II) another set of levels [m;(2m-1)] containing the same number of levels (m) as the first set;
    reiterating (N R - 1 times) the reprogramming without erasing phase (III,IV, ...) until the levels (N) of the multilevel cell are exhausted.

    The invention makes also reference to a multilevel memory device of the type comprising a plurality. of multilevel memory cells organised into sectors, the sectors being themselves split into a plurality of data units (UD) wherein a data updating operation is performed in parallel, the data units (UD) being programmed by means of the programming method according to the invention.

    Abstract translation: 本发明涉及一种能够存储多个级别（N）中的多个位的多级存储器单元的编程方法，该方法包括以下阶段：首先将单元阈值（VthDATI）编程（I）到第一 层级ÄO;（m-1）Ü是（m）多级单元的多（N）个级别中的一个子; 重新编程而不擦除（II）另一组水平Äm;（2m-1）Ü包含与第一组相同数量的水平（m）; 重复（NR-1次）重编程而不擦除相位（III，IV，...），直到多级单元的电平（N）耗尽。 本发明还涉及包括多个类型的多级存储器件。 的多级存储器单元被组织成扇区，扇区本身被分成多个数据单元（UD），其中并行执行数据更新操作，数据单元（UD）通过根据本发明的编程方法进行编程 。

    Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method
    8.
    发明公开
    Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method 有权
    擦除和用于存储块并行重新写入电路，尤其是对于模拟快闪单元，和它们的操作

    公开(公告)号：EP1065668A1

    公开(公告)日：2001-01-03

    申请号：EP99830381.2

    申请日：1999-06-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Guaitini, Giovanni ,  Rolandi, Pier Luigi

    IPC: G11C16/08 ,  G11C8/00

    CPC classification number: G11C8/10 ,  G11C16/08

    Abstract: Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, characterized in that it comprises at least one row decoding circuit (5, 7) comprising at least two adder blocks (31), suitable to generate a row address signal (32), at least two decoder blocks (33), suitable to generate respective pluralities of signals (34, 35, 36, 37; 42, 43, 44, 45) identifying a respective sector of memory to be enabled, at least two shifter blocks (38), suitable to generate an address signal (48, 49) of another row to be enabled, at least two OR logic blocks (39), suitable to generate respective signals (40; 41) serving the purpose to simultaneously enable at least two rows of the memory matrix (1).

    Abstract translation: 电路用于擦除和重写的存储单元和特别模拟闪存单元，在做了它包括至少一个行解码电路，其特征的块（5,7）包括至少两个加法器块（31），适合于生成的行地址信号（ 32），至少两个解码器块（33）适合于产生的信号（34，35，36，37 respectivement多个;启用识别的存储器中的扇区respectivement 42，43，44，45），至少两个移动器 块（38）适合于产生对另一行的地址信号（48，49）被使能，至少两个OR逻辑块（39）适于产生respectivement信号（40; 41）服务的目的为能够同时在 存储器矩阵的至少两排（1）。

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