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    Nonvolatile memory device, in particular of flash type
    2.
    发明公开
    Nonvolatile memory device, in particular of flash type 有权
    NichtflüchtigeSpeicheranordnung，insbesondere vom Flash-Typ

    公开(公告)号：EP1063653A1

    公开(公告)日：2000-12-27

    申请号：EP99830396.0

    申请日：1999-06-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Zammattio, Matteo ,  Campardo, Giovanni

    IPC: G11C16/16 ,  G11C16/08

    CPC classification number: G11C8/12 ,  G11C16/12

    Abstract: The memory device (21) has hierarchical sector decoding (24, 25). A plurality of groups of supply lines (28-32) is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages (35) are each connected between a respective sector (15) and a respective group of supply lines (28-32); the switching stages (35) connected to sectors (15) arranged on a same column are controlled by same control signals (S0, S1) supplied on control lines (40) extending parallel to the columns of sectors. For biasing the sectors, modification voltages (NW, SB, V NEG ) are sent to at least one selected group of biasing lines (28-32), and control signals (SO, S1) are sent to the switching stages connected to a selected sector column.

    Abstract translation: 存储器件（21）具有分级扇区解码（24,25）。 提供多组供应线（28-32），每个扇区行一个平行于扇区行延伸。 多个开关级（35）分别连接在相应的扇区（15）和相应的一组供电线（28-32）之间。 连接到布置在同一列上的扇区（15）的开关级（35）由与扇区列平行延伸的控制线（40）上提供的相同控制信号（S0，S1）控制。 为了偏置扇区，将修改电压（NW，SB，VNEG）发送到至少一组选定的偏置线（28-32），并且控制信号（SO，S1）被发送到连接到所选扇区的开关级 柱。

    Method and circuit for regulating the length of an ATD pulse signal
    5.
    发明公开
    Method and circuit for regulating the length of an ATD pulse signal 失效
    Verfahren und Schaltung zur Regulierung derLängeeinesAdressenübergangssignalsATD

    公开(公告)号：EP0915476A1

    公开(公告)日：1999-05-12

    申请号：EP97830573.8

    申请日：1997-11-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Zammattio, Matteo ,  Ferrario, Donato

    IPC: G11C8/00 ,  G11C7/00

    CPC classification number: G11C8/18

    Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier.
    The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

    Abstract translation: 本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。 在检测到存储单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便也产生到读出放大器的均衡信号（SAEQ）。 当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。 有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。

    Temperature correlated voltage generator circuit and corresponding voltage regulator for a single power memory cell, particularly of the FLASH-type
    6.
    发明公开
    Temperature correlated voltage generator circuit and corresponding voltage regulator for a single power memory cell, particularly of the FLASH-type 失效
    温度相关电压发生器电路和用于提供与单个电源上的存储器单元相关联的电压调节器，特别是闪存类型的

    公开(公告)号：EP0915407A1

    公开(公告)日：1999-05-12

    申请号：EP97830574.6

    申请日：1997-11-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mulatti, Jacopo ,  Zammattio, Matteo ,  Ghilardelli, Andrea ,  Carrera, Marcello

    IPC: G05F1/00 ,  G05F3/24

    CPC classification number: G05F3/245 ,  Y10S323/907

    Abstract: The invention relates to a temperature-related voltage generating circuit having an input terminal (15) receiving a control voltage (V BG ) independent of temperature, and an output terminal (16) delivering a temperature-related control voltage (Vout), the input and output terminals (15, 16) being connected together through at least an amplifier stage (19) adapted to set an output reference voltage from a comparison of input voltages, and comprising a generator element (T1) generating a Varying voltage (V BE ) with temperature connected between a ground voltage reference (GND) and a non-inverting input terminal of the amplifier stage (19), which has an output terminal adapted to deliver a multiple of the varying voltage (V BE ) with temperature to an inverting input terminal of a comparator stage (18); the comparator stage (18) has its output connected to the temperature-related voltage generating circuit (14) and a non-inverting input terminal receiving the control voltage (V BG ) independent of temperature to evaluate the difference between the control voltage (V BG ) independent of temperature and said voltage being a multiple of the varying voltage (V BE ) with temperature and to output a temperature-related control voltage (Vout) having at room temperature a mean value which is independent of its thermal differential (δVout/δT) and increases with temperature.
    The invention also relates to a regulator for a drain voltage (Vd) of a single-supply memory cell (M1), comprising a temperature-related voltage generating circuit (14) according to the invention.

    Abstract translation: 本发明涉及具有输入端子（15）的温度相关的电压生成电路接收控制电压（VBG）与温度无关，并提供一个温度相关的控制电压（Vout），所述输入输出端子（16）和 输出端子（15，16）通过连接在一起的至少到放大器级（19）angepasst从输入电压的比较，并包括发电机元件（T1）产生变化的电压（VBE）与温度设定为输出参考电压 连接在地电压基准（GND）和所述放大器级（19），其具有与输出端子angepasst以反转的输入端子提供变化的电压（VBE）随温度的倍数的一个非反相输入端之间 比较器级（18）; 的比较器级（18）具有其输出连接到所述温度有关的电压发生电路（14）和一个非反相输入端接收与温度无关的控制电压（VBG），以评估（VBG）独立于控制电压之间的差 温度和所述电压是所述变化的电压（VBE）的随温度和输出的平均值的所有其是独立于其热差异的（增量比Vout /增量T）在室温下具有的温度相关的控制电压（Vout）的倍数的 随着温度增加而增加。 因此，本发明涉及一种用于一个温度相关的电压发生电路（14）的单电源的存储单元（M1）的漏极电压（Vd）的调节器雅丁于本发明。

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