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公开(公告)号：KR1020120127033A
公开(公告)日：2012-11-21
申请号：KR1020110045238
申请日：2011-05-13
Applicant: 전자부품연구원
CPC classification number: H01L21/568 , H01L2224/04105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2924/15153 , H01L2924/181 , H01L2924/00 , H01L2224/18 , H01L2924/00012
Abstract: PURPOSE: A manufacturing method for a chip embedded substrate is provided to easily arrange a semiconductor chip in an semiconductor chip inlet hole by precisely making the semiconductor chip inlet hole using a dry film. CONSTITUTION: A photosensitive dry film(200) for mounting a semiconductor chip is laminated on an upper portion of a metal thin film(100). The photosensitive dry film for an alignment pattern is laminated on a lower portion of the metal thin film. A semiconductor chip inlet hole is formed for inserting the semiconductor chip into the photosensitive dry film for mounting the semiconductor chip. An alignment pattern is formed on the photosensitive dry film for the alignment pattern. An alignment post is formed by etching the metal thin film except for a portion where the alignment pattern is formed.
Abstract translation: 目的：提供一种用于芯片嵌入式基板的制造方法，通过使用干膜精确地制造半导体芯片入口孔，将半导体芯片容易地布置在半导体芯片入口孔中。 构成：用于安装半导体芯片的感光干膜（200）层压在金属薄膜（100）的上部。 用于对准图案的感光性干膜层叠在金属薄膜的下部。 形成用于将半导体芯片插入到用于安装半导体芯片的感光干膜中的半导体芯片入口孔。 在对准图案的感光性干膜上形成取向图案。 通过蚀刻除了形成对准图案的部分之外的金属薄膜形成定位柱。
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公开(公告)号：KR1020120078686A
公开(公告)日：2012-07-10
申请号：KR1020120056923
申请日：2012-05-29
Applicant: 전자부품연구원
CPC classification number: H01L2224/24 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: A semiconductor package and a manufacturing method thereof are provided to perform a through via with low loss, a high frequency passive device with high performance and a transmission line on a silicon substrate. CONSTITUTION: A first hole is formed on a silicon substrate(S110). A first metal layer is formed on the silicon substrate formed the first hole(S115). An insulating layer is formed on the first metal layer(S120). A second hole which size is smaller than the first hole size is formed at the first hole position(S130). A second metal layer is formed on the insulating layer by filing the second hole(S140). The first metal layer and the second metal layer are exposed to the lower surface of the silicon substrate(S150).
Abstract translation: 目的：提供一种半导体封装及其制造方法，以低损耗执行通孔，具有高性能的高频无源器件和硅衬底上的传输线。 构成：在硅衬底上形成第一孔（S110）。 在形成第一孔的硅衬底上形成第一金属层（S115）。 在第一金属层上形成绝缘层（S120）。 在第一孔位置处形成尺寸小于第一孔尺寸的第二孔（S130）。 通过填充第二孔而在绝缘层上形成第二金属层（S140）。 第一金属层和第二金属层暴露于硅基板的下表面（S150）。
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公开(公告)号：KR1020120072451A
公开(公告)日：2012-07-04
申请号：KR1020100134210
申请日：2010-12-24
Applicant: 전자부품연구원
CPC classification number: H01L2224/04105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/14 , H01L2924/00 , H01L2224/18 , H01L2924/00012
Abstract: PURPOSE: A multilayer semiconductor device and a manufacturing method thereof are provided to prevent voids by connecting signal lines between unit semiconductor packages using a metal pin insertion method. CONSTITUTION: A top unit semiconductor package(200) is formed on a bottom unit semiconductor package(100). An organic layer(230) is formed on the lower side of the top unit semiconductor package. A metal pin(130) of the bottom unit semiconductor package is inserted into a hole of the top unit semiconductor package. An insulation layer(240) is formed between the metal pin and a silicon substrate(210). A top unit semiconductor package(300) is stacked on the top unit semiconductor package.
Abstract translation: 目的：提供一种多层半导体器件及其制造方法，以通过使用金属针插入方法连接单元半导体封装之间的信号线来防止空隙。 构成：顶部单元半导体封装（200）形成在底部单元半导体封装（100）上。 在顶部单元半导体封装的下侧形成有机层（230）。 底部单元半导体封装的金属引脚（130）插入到顶部单元半导体封装的孔中。 在金属销和硅衬底（210）之间形成绝缘层（240）。 顶部单元半导体封装（300）堆叠在顶部单元半导体封装上。
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公开(公告)号：KR101139719B1
公开(公告)日：2012-04-26
申请号：KR1020100101209
申请日：2010-10-18
Applicant: 전자부품연구원
Abstract: PURPOSE: A contactless tag antenna for attachment to a metallic surface is provided to increase sensing distance in comparison with general label tag and a metal tag by high gain. CONSTITUTION: A contactless tag antenna has meandered folded-dipole structure. The contactless tag antenna comprises a first conductive trace part(10), a second conductive trace part(20), a T-shaped matching part(30), and a loop part(40). The first conductive trace part is formed symmetrically to the second conductive trace part based on the T-shaped matching part. One end of the first conductive trace part is connected to the T-shaped matching part. The other end of the first conductive trace part is connected to the second conductive trace part.
Abstract translation: 目的：提供一种用于连接到金属表面的非接触式标签天线，以增加与普通标签标签和金属标签相比较高增益的感应距离。 构成：非接触式标签天线具有蜿蜒的折叠偶极子结构。 非接触式标签天线包括第一导电迹线部分（10），第二导电迹线部分（20），T形匹配部分（30）和环形部分（40）。 第一导电迹线部分基于T形匹配部分对称地形成于第二导电迹线部分。 第一导电迹线部分的一端连接到T形匹配部分。 第一导电迹线部分的另一端连接到第二导电迹线部分。
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公开(公告)号：KR101135394B1
公开(公告)日：2012-04-17
申请号：KR1020100039810
申请日：2010-04-29
Applicant: 전자부품연구원
IPC: H04W24/06
Abstract: PURPOSE: A device for testing a wireless module and a system thereof are provided to inspect standardization related to the performance of a wireless module by using the mounted measuring module. CONSTITUTION: A unit for operating a universal spectrum measurement module(121) can mount a universal spectrum measurement module. The universal spectrum measurement module obtains a measurement result by measuring the performance of a wireless module. A unit for operating a high precision spectrum measurement module can mount the high precision spectrum measurement module(122). The high precision spectrum measuring module obtains a measuring result by measuring the performance of the wireless module. A standardized inspection unit(140) inspects whether the performance of the wireless module satisfies the standards based on a measuring result of a measuring module which is mounted in at least one between the unit for operating a universal spectrum measurement module and the unit for operating a high precision spectrum measurement module.
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Patent Agency Ranking
公开(公告)号：KR101104134B1
公开(公告)日：2012-01-13
申请号：KR1020090104542
申请日：2009-10-30
Applicant: 전자부품연구원
Abstract: 반도체 칩 패키징 방법이 개시된다. 본 발명에 따른 반도체 칩 패키징 방법은 다이싱 테잎(tape)에 웨이퍼를 부착시켜 다이싱하고, 다이싱된 칩(diced chip) 영역을 커버하는 노광부위를 포함하는 포토마스크를 통해 다이싱 테잎을 노광시켜 기판 상에 칩 부착영역을 정의하도록 노광시킨다. 다이싱 테잎을 기판과 접촉시켜 노광부위에 대응하는 칩을 기판의 칩 부착영역에 부착시킨다. 그 후, 다이싱 테잎이 부착된 칩이 포토마스크의 노광부위에 대응되도록 다이싱 테잎을 일정한 간격만큼 이동시킨다. 이에 따라 초소형 반도체 칩의 패키징 공정시간을 단축시킬 수 있다.
다이싱 테잎(Dicing Tape), 포토마스크(Photomask)-
公开(公告)号：KR1020110119210A
公开(公告)日：2011-11-02
申请号：KR1020100038797
申请日：2010-04-27
Applicant: 전자부품연구원
CPC classification number: H04B1/48
Abstract: PURPOSE: A front end module for local area wireless communication and manufacturing method thereof are provided to embed a power amplifier and a switch inside a printed circuit board in one layer structure. CONSTITUTION: The inside of a substrate is included of one structure. A first circuit block(120) is embedded inside the substrate. The first circuit block is implemented in an integrated circuit type. A second circuit block(140) is embed with the first circuit block inside the substrate.
Abstract translation: 目的：提供一种用于局域无线通信的前端模块及其制造方法，以将功率放大器和开关嵌入印刷电路板的一层结构中。 构成：一个结构中包括一个衬底的内部。 第一电路块（120）嵌入衬底内。 第一电路块以集成电路类型实现。 第二电路块（140）与第一电路块嵌入衬底内。
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公开(公告)号：KR1020110076517A
公开(公告)日：2011-07-06
申请号：KR1020090133258
申请日：2009-12-29
Applicant: 전자부품연구원
IPC: H01P1/207
CPC classification number: H01P1/207 , H01P1/203 , H01P3/08 , H01P11/007
Abstract: PURPOSE: An SIW(Surface Integrated Waveguide) filter embedded in a substrate and a manufacturing method thereof are provided to implement the integration of a system and reduce the weight and size of the device by embedding the SIW filter in the substrate. CONSTITUTION: An SIW filter(100) is formed in an inner layer(60) of a substrate(200). A via(70) is formed between the inner layers of the substrate and a surface layer(50) of the substrate. A correction circuit(80) corrects the distortion of inductance elements due to via. The correction circuit is composed of one series line and two shunt stub lines. The series line is formed on both sides of the correction circuit.
Abstract translation: 目的：提供嵌入基片中的SIW（表面积波导）滤波器及其制造方法，以实现系统的集成，并通过将SIW滤波器嵌入到基片中来减小器件的重量和尺寸。 构成：在衬底（200）的内层（60）中形成SIW过滤器（100）。 在衬底的内层和衬底的表面层（50）之间形成通孔（70）。 校正电路（80）校正由于通孔导致的电感元件的失真。 校正电路由一个串联线和两个分路短线组成。 串联线形成在校正电路的两侧。
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公开(公告)号：KR1020110021025A
公开(公告)日：2011-03-04
申请号：KR1020090078568
申请日：2009-08-25
Applicant: 전자부품연구원
CPC classification number: H01L2224/16225 , H01L2924/19105
Abstract: PURPOSE: An active/passive component built-in substrate manufacturing method is provided to remove the additional resin filling process by allowing the easy polymer filling even when the gap between devices is too narrow. CONSTITUTION: An active/passive component built-in substrate manufacturing method forms a polymer layer(102) of half hardened state on the bottom copper film. A polymer core(103) is deposited on the polymer layer. The polymer core has a cavity in which the active/passive devices(105, 107) are installed inside.
Abstract translation: 目的：提供一种内置有源/无源器件的衬底制造方法，以便即使在器件之间的间隙太窄时也允许容易的聚合物填充来除去额外的树脂填充过程。 构成：主动/被动元件内置衬底制造方法在底部铜膜上形成半硬化状态的聚合物层（102）。 聚合物芯（103）沉积在聚合物层上。 聚合物芯具有其中主动/被动装置（105,107）安装在其中的空腔。
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公开(公告)号：KR100963201B1
公开(公告)日：2010-06-16
申请号：KR1020080023454
申请日：2008-03-13
Applicant: 전자부품연구원
CPC classification number: H01L24/82 , H01L2224/04105 , H01L2224/19 , H01L2224/32245 , H01L2224/73267 , H01L2224/8203 , H01L2224/92144 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/18162 , H01L2224/18 , H01L2924/00012
Abstract: 본 발명은 칩 내장형 기판 및 그의 제조 방법에 관한 것으로, 금속박에 미리 관통홀들을 형성하여, 칩과 관통홀들의 정렬을 정밀 및 신속하게 할 수 있어, 칩 내장형 기판의 제조 수율을 향상시킬 수 있게 된다.
더불어, 본 발명은 칩의 열 팽창 계수와 금속박의 열팽창 계수 사이의 열팽창 계수를 갖는 물질로 금속박과 칩을 접착함으로써, 칩과 금속박의 열팽창 계수의 차이로 인한 신뢰성 저하를 감소시킬 수 있는 장점이 있는 것이다.
칩, 동박, 관통홀, 내장, 접착, 정렬Abstract translation: 提供了基板嵌入式芯片及其制造方法，以减少由于芯片和金属膜的热膨胀系数的差异导致的可靠性劣化。 在金属膜（100）图案中形成多个贯通孔。 具有输入输出端子（210）的芯片（200）被粘附到金属膜图案上，并且形成在对应于多个穿透孔的位置。 密封剂（400）围绕芯片并形成在金属膜的上部。 焊盘（511,512,513）通过多个贯穿孔连接到输入输出端子。 在密封剂中形成有多个贯通孔。 密封剂覆盖散热部分的至少一部分。
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