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公开(公告)号：KR1020050071954A
公开(公告)日：2005-07-08
申请号：KR1020040000357
申请日：2004-01-05
Applicant: 한국과학기술연구원
IPC: H01L21/8239
Abstract: 본 발명은 상변화 물질의 접촉면적을 최대한 줄임으로써 저전력 및 고집적 특성을 갖는 상변화 물질을 이용한 상변화 메모리 및 그 제조방법에 관한 것이다. 이를 위해, 본 발명은 절연막/하부전극/기판에 상변화 물질을 증착하고 건식 식각을 통해 수직으로 에칭하여 절연막/하부전극의 벽면을 따라 상변화 물질의 스페이서가 형성되도록 하여 하부전극의 두께로 상변화 물질의 접촉면적이 결정될 수 있도록 한다. 또한, 트렌치 구조의 내부에 하부전극을 형성하고 상변화 물질을 증착한 후 건식 식각을 통해 수직으로 에칭하여 절연막의 벽면을 따라 상변화 물질의 스페이서가 형성되도록 하여 상변화 물질의 두께로 상변화 물질의 접촉면적이 결정될 수 있도록 한다.
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92.发明公开식각 선택비가 큰 버퍼층을 이용한 자기정렬 강유전체게이트 트랜지스터의 제조방법 失效使用具有高选择性的缓冲层制造自对准的电磁栅极晶体管的方法可以在防止硅衬底损坏的情况下增加自对准的电介质栅极晶体管的集成
公开(公告)号：KR1020050021095A
公开(公告)日：2005-03-07
申请号：KR1020030059188
申请日：2003-08-26
Applicant: 한국과학기술연구원
IPC: H01L27/105
CPC classification number: H01L29/6684 , H01L21/2652 , H01L21/28291 , H01L29/66575
Abstract: PURPOSE: A method for fabricating a self-aligned ferroelectric gate transistor using a buffer layer with high etch selectivity is provided to increase integration of a self-aligned ferroelectric gate transistor while preventing a silicon substrate from being damaged by performing a dry etch process after a buffer layer with high etch selectivity is interposed between the silicon substrate and a ferroelectric layer. CONSTITUTION: A buffer layer(2) made of a material with high etch selectivity is formed on a silicon substrate(1). A ferroelectric layer and an upper electrode are formed on the buffer layer. The ferroelectric layer and the upper electrode except a portion corresponding to a gate(5) are etched. An etch process stops in the buffer layer. A source/drain is formed in a portion etched by an ion implantation process.
Abstract translation: 目的：提供使用具有高蚀刻选择性的缓冲层制造自对准铁电栅极晶体管的方法，以增加自对准铁电栅极晶体管的集成，同时防止硅衬底在经过干法蚀刻工艺之后被损坏 在硅衬底和铁电层之间插入具有高蚀刻选择性的缓冲层。 构成：在硅衬底（1）上形成由具有高蚀刻选择性的材料制成的缓冲层（2）。 在缓冲层上形成铁电体层和上部电极。 除了对应于栅极（5）的部分之外的铁电层和上电极被蚀刻。 蚀刻工艺在缓冲层中停止。 在通过离子注入工艺蚀刻的部分中形成源极/漏极。
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公开(公告)号：KR1020030080416A
公开(公告)日：2003-10-17
申请号：KR1020020019017
申请日：2002-04-08
Applicant: 한국과학기술연구원
IPC: H01L21/205
Abstract: PURPOSE: A thin film depositing method using pulse plasma discharge is provided to be capable of effectively transforming reaction gas into plasma by using a pulse plasma production apparatus. CONSTITUTION: After transforming reaction gas A into the first plasma using a pulse plasma production apparatus, the first thin film is deposited at the upper portion of a wafer by flowing the first plasma into a thin film depositing apparatus. Then, the first plasma is exhausted by using purge gas. After transforming reaction gas B into the second plasma, the second thin film is deposited on the first thin film. Then, the second plasma is exhausted by using the purge gas. The pulse plasma production apparatus is provided with a power supply(21), a slide transformer(22) for decreasing the voltage supplied from the power supply, a high voltage transformer(23) for increasing the voltage supplied from the slide transformer, a load(25) for generating plasma by using the voltage supplied from the high voltage transformer, and a rotating spark gap switch(24) for connecting the high voltage transformer with the load.
Abstract translation: 目的：使用脉冲等离子体放电的薄膜沉积方法能够通过使用脉冲等离子体生产设备来有效地将反应气体转化成等离子体。 构成：使用脉冲等离子体生产装置将反应气体A转换成第一等离子体后，通过使第一等离子体流入薄膜沉积装置，将第一薄膜沉积在晶片的上部。 然后，通过使用吹扫气体排出第一等离子体。 在将反应气体B转化成第二等离子体之后，第二薄膜沉积在第一薄膜上。 然后，通过使用净化气体排出第二等离子体。 脉冲等离子体制造装置设置有电源（21），用于降低从电源供给的电压的滑动变压器（22），用于增加从滑动变压器供给的电压的高压变压器（23），负载 （25），用于通过使用从高压变压器提供的电压产生等离子体;以及用于将高压变压器与负载连接的旋转火花隙开关（24）。
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公开(公告)号：KR1020020084524A
公开(公告)日：2002-11-09
申请号：KR1020010023860
申请日：2001-05-02
Applicant: 한국과학기술연구원
IPC: B64C11/20
CPC classification number: Y02T50/44
Abstract: PURPOSE: A subminiature helicopter is provided to promote the manufacturing by making the structure and shape simplified and to precisely measure aeromechanic characteristic value of a subminiature helicopter. CONSTITUTION: A subminiature helicopter comprises a pair of blades(2) having sections of an airfoil shape, a rotor device(4) for giving driving force for rotation of the blades, a guide device, and a power source supply unit(10) for applying power source to the rotor device. The guide device prevents rotation of the rotor device and makes rectilinear movement of the rotor device possible together when the rotor device moves up and down by rotation of the blades. The guide device comprises a guide bracket(6) and a guide rod(8). The guide bracket is installed on the outer surface of the rotor device for rectilinear movement of the rotor device. The guide rod is installed vertically to guide the guide bracket up and down. The guide bracket comprises a pair of guide connection units extended from the rotor device and guide pipes installed to the upper and lower side of both ends of the guide connection units to reduce the weight of the helicopter.
Abstract translation: 目的：提供超小型直升机，通过使结构和形状简化，精确测量超小型直升机的机械特性值来促进制造。 构成：超小型直升机包括具有翼型形状的一对叶片（2），用于产生用于叶片旋转的驱动力的转子装置（4），导向装置和电源装置（10），用于 将电源施加到转子装置。 引导装置防止转子装置的旋转，并且当转子装置通过叶片的旋转而上下移动时，使转子装置的直线运动成为可能。 导向装置包括导向支架（6）和导杆（8）。 导向支架安装在转子装置的外表面上，用于转子装置的直线运动。 引导杆垂直安装，上下引导引导支架。 引导支架包括从转子装置延伸的一对引导连接单元和安装到引导连接单元两端的上侧和下侧的引导管，以减小直升机的重量。
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公开(公告)号：KR1020020005218A
公开(公告)日：2002-01-17
申请号：KR1020000036003
申请日：2000-06-28
Applicant: 한국과학기술연구원
IPC: H01L27/115
Abstract: PURPOSE: A method for manufacturing a memory cell device of a non-destructive readout non-volatile memory device is provided to decrease an operation voltage, by forming a transistor of a metal/YMNO3/Si gate structure so that the voltage applied to a ferroelectric is remarkably increased at a low operation voltage and the voltage across an oxide layer can be decreased. CONSTITUTION: Y/Mn mole density is controlled to maintain a Y/Mn composition ratio from 21/15 to 8/14 so that a YMnO3 ferroelectric thin film of a transistor gate having a metal/ferroelectric/semiconductor structure is deposited by a metal organic decomposition(MOD) method.
Abstract translation: 目的：提供一种用于制造非破坏性读出非易失性存储器件的存储单元器件的方法，通过形成金属/ YMNO3 / Si栅极结构的晶体管来降低工作电压，使得施加到铁电体 在低操作电压下显着增加，并且可以降低跨越氧化物层的电压。 构成：控制Y / Mn摩尔浓度以使Y / Mn组成比从21/15至8/14保持，使得具有金属/铁电/半导体结构的晶体管栅极的YMnO 3铁电薄膜通过金属有机物 分解（MOD）方法。
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Patent Agency Ranking
公开(公告)号：KR100279052B1
公开(公告)日：2001-02-01
申请号：KR1019970057883
申请日：1997-11-04
Applicant: 한국과학기술연구원
IPC: H01L29/78 , H01L27/115
Abstract: 반도체표면에 CeO
2 /SrBi
2 Ta
2 O
9 이중막을 형성시키고 이중막의 강유전체인 SrBi
2 Ta
2 O
9 막상에 백금전극을 부착하며, 상기 CeO
2 /SrBi
2 Ta
2 O
9 /Pt의 삼중층 주위에 산화방지막을 도포하여 형성되는 게이트를, 전계효과트랜지스터의 게이트로 이용하므로서 커패시터가 필요없는 강유전체게이트를 가지는 전계효과트랜지스터(FET)기억소자를 제공한다.-
公开(公告)号：KR1019970004424B1
公开(公告)日：1997-03-27
申请号：KR1019930028840
申请日：1993-12-21
Applicant: 한국과학기술연구원
IPC: H01L21/20
Abstract: The method for in creasing crystallinity of manufactured thin film includes steps; a) increasing temp. of specimen up to deposition one with lamp heater ; b) depositing thin film on surface of the specimen by spraying deposition reacting material ; and c) rotating specimen 180 degree to face the thin film to the lamp heater such that the light of the lamp heater radiates to surface of the thin film directly.
Abstract translation: 制造薄膜的结晶度降低的方法包括以下步骤： a）增加温度 的样品直到用灯加热器沉积; b）通过喷涂沉积反应材料在试样的表面上沉积薄膜; 以及c）将样品180度旋转以面对所述薄膜到所述灯加热器，使得所述灯加热器的光直接辐射到所述薄膜的表面。
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公开(公告)号：KR100081643B1
公开(公告)日：1995-01-20
申请号：KR1019910011618
申请日：1991-07-09
Applicant: 한국과학기술연구원
IPC: H01L21/285
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公开(公告)号：KR100072153B1
公开(公告)日：1994-03-23
申请号：KR1019910012125
申请日：1991-07-16
Applicant: 한국과학기술연구원
IPC: H01L21/285
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公开(公告)号：KR1019930022471A
公开(公告)日：1993-11-24
申请号：KR1019920005596
申请日：1992-04-03
Applicant: 한국과학기술연구원
IPC: H01L21/28
Abstract: 본 발명은 플라즈마 화학증착법을 이용하여 갈륨비소 반도체소자의 금속배선용 텡스텐박막을 증착시키는 방법에 관한 것이다.
본 발명은 갈륨비소기판을 일반적인 PECVD반응기내에 위치시킨 상태에서 WF
6 -SiH
4 -H
2 반응계를 이용하여 중착압력 1-10
-1 Torr, 중착온도 200∼300℃에서 금속배선용 텡스텐박막을 갈륨비소 기판의 표면에 중착히키는 방법으로 이루어져 있다.
본 발명은 종래의 알루미늄등을 쇼트키 콘택트(Schottky contact)용 금속박막으로 사용하는 경우에 야기되는 열처리에 따른 결함이 억제되고, 특히 자기정렬 MESFET제조시 그 제조공정의 단순화가 가능해진다는 장점이 있다.
그리고, 본 발명의 방법에 의해 얻어지는 텡스텐박막은 비저항이 약 20 πΩ-㎝이고 낮은 역방향 누설전류특성을 나타낸다.
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