公开(公告)号：US20240206061A1

公开(公告)日：2024-06-20

申请号：US18537877

申请日：2023-12-13

Applicant: IBIDEN CO., LTD.

Inventor： Ryo ANDO ,  Nobuhisa KURODA ,  Shogo FUKUI ,  Kosei ICHIKAWA ,  Makoto KATO

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H05K1/0373 ,  H05K1/0298 ,  H05K2201/0209 ,  H05K2201/0254 ,  H05K2201/0269

Abstract: A wiring substrate includes an insulating layer including a first layer and a second layer, and a conductor layer including a metal film formed on a surface of the second layer of the insulating layer such that the conductor layer includes a conductor pattern. The first layer includes resin and first inorganic particles, the second layer includes resin and second inorganic particles at the content rate that is lower than the content rate of the first inorganic particles in the first layer, and the thickness of the first layer is 90% or more of the thickness of the insulating layer. The second layer of the insulating layer includes a composite layer having the thickness in the range of 0.1 to 0.3 μm, and the composite layer includes part of the metal film in the conductor layer formed in gaps between the second inorganic particles and resin in the second layer.

公开(公告)号：US09918381B2

公开(公告)日：2018-03-13

申请号：US14588614

申请日：2015-01-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoru Noda

IPC: H05K1/18 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H05K3/28 ,  H05K3/46 ,  H05K1/03 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/0271 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/0373 ,  H05K1/186 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/0347 ,  H05K2201/09136 ,  H05K2201/10636 ,  H05K2203/0126 ,  H05K2203/0465 ,  H05K2203/085 ,  H05K2203/1316 ,  H05K2203/1322 ,  Y02P70/611

Abstract: A component-embedded substrate includes a substrate portion, an embedded electronic component, and a resin portion. The substrate portion has inner electrodes on an inner principal surface. The embedded electronic component has terminal electrodes and is mounted to the substrate portion via solder fillets adhering to the respective terminal electrodes and the respective inner electrodes. The resin portion is stacked on the substrate portion, with the embedded electronic component embedded therein. The resin portion includes a no-filler-added layer and a filler-added layer. The no-filler-added layer extends from the inner principal surface to a height which allows at least the solder fillets to be covered. The filler-added layer contains an inorganic filler and extends from an interface with the no-filler-added layer to a height which allows at least the embedded electronic component to be covered.

公开(公告)号：US20170347449A1

公开(公告)日：2017-11-30

申请号：US15536954

申请日：2015-12-18

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Motohiko SUGIURA ,  Takashi KASUGA ,  Yoshio OKA ,  Shigeaki UEMURA ,  Jinjoo PARK ,  Hiroshi UEDA ,  Kousuke MIURA

IPC: H05K1/09 ,  H05K3/24 ,  H05K1/03 ,  H05K1/02 ,  H05K3/38 ,  H05K1/05 ,  B82Y30/00

CPC classification number: H05K1/097 ,  B82Y30/00 ,  B82Y40/00 ,  H05K1/0298 ,  H05K1/03 ,  H05K1/05 ,  H05K1/09 ,  H05K3/24 ,  H05K3/38 ,  H05K3/388 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0266 ,  H05K2201/0269

Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a metal layer formed on at least one surface side of the base film. In the substrate for a printed circuit board, a plurality of fine particles are disposed between the base film and the metal layer, and the fine particles are formed of a metal the same as a main metal of the metal layer or formed of a metal compound of the main metal. The fine particles preferably have an average particle size of 0.1 nm or more and 20 nm or less. The fine particles are preferably formed of a metal oxide or a metal hydroxide. The fine particles are preferably present between the base film and the metal layer so as to form a layer. The metal layer preferably includes a metal grain layer formed by firing metal nanoparticles.

公开(公告)号：US09423691B2

公开(公告)日：2016-08-23

申请号：US14658684

申请日：2015-03-16

Applicant: TAIYO HOLDINGS CO., LTD.

Inventor： Takahiro Yoshida ,  Shouji Minegishi ,  Masao Arima

IPC: G03F7/004 ,  G03F7/095 ,  H05K3/28

CPC classification number: G03F7/095 ,  G03F7/004 ,  G03F7/0047 ,  H05K3/285 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068

Abstract: In a layered structure having at least a substrate and a photosensitive resin layer or cured film layer formed on the substrate and containing an inorganic filler, the content of the inorganic filler in the photosensitive resin layer or cured film layer is low on the side contacting the substrate and high on the surface side away from the substrate, so that a linear thermal expansion coefficient of the photosensitive resin layer or cured film layer as a whole is maintained as low as possible. Preferably, the inorganic filler content in the layer gradually increases continuously obliquely or stepwise from the side contacting the substrate to the surface side away from the substrate. A photosensitive dry film containing the above-mentioned photosensitive resin layer is suitable for use as a solder resist or an interlayer resin insulation layer of a printed wiring board.

公开(公告)号：US20160047767A1

公开(公告)日：2016-02-18

申请号：US14460598

申请日：2014-08-15

Applicant: John Andrew Lebens ,  Ronald Steven Cok ,  Yongcal Wang

Inventor： John Andrew Lebens ,  Ronald Steven Cok ,  Yongcal Wang

IPC: G01N27/12

CPC classification number: G01N27/126 ,  G01N27/07 ,  G02F1/13439 ,  G06F3/044 ,  G06F2203/04103 ,  H05K3/0014 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0112 ,  H05K2201/0257 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/2054 ,  H05K2203/0108 ,  H05K2203/1131 ,  H05K2203/1476

Abstract: A method of operating an imprinted electronic sensor to sense an environmental factor includes providing spatially separated micro-channels in a cured layer on a substrate. A multi-layer micro-wire is formed in each micro-channel. Each multi-layer micro-wire includes at least a conductive layer and a reactive layer exposed to the environmental factor. The conductive layer is a cured electrical conductor located only within the micro-channel and at least a portion of the reactive layer responds to the environmental factor. A controller is provided for electrically controlling first and second groups of multi-layer micro-wires, each first and second group including one or more multi-layer micro-wires. The reactive layer is exposed to the environment. The controller measures the electrical response of the first and second groups of multi-layer micro-wires. The electrical response includes at least one of the amperometric response, the resistance, the capacitance, the impedance, the complex impedance, or the inductance.

Abstract translation: 操作印刷电子传感器以感测环境因素的方法包括在基板上的固化层中提供空间分离的微通道。 在每个微通道中形成多层微线。 每个多层微线包括至少暴露于环境因素的导电层和反应层。 导电层是仅位于微通道内的固化电导体，并且反应层的至少一部分响应于环境因素。 提供一种用于电控制第一组和第二组多层微线的控制器，每个第一组和第二组包括一个或多个多层微线。 反应层暴露于环境中。 控制器测量第一组和第二组多层微线的电响应。 电响应包括电流响应，电阻，电容，阻抗，复阻抗或电感中的至少一个。

公开(公告)号：US09161444B2

公开(公告)日：2015-10-13

申请号：US14354600

申请日：2012-09-28

Applicant: KYOCERA Corporation

Inventor： Kiyotaka Nakamura ,  Yoshio Ohashi ,  Kunihide Shikata

IPC: H05K1/00 ,  H05K1/09 ,  H05K3/38 ,  H01L23/15 ,  C04B41/90 ,  C04B41/00 ,  C04B41/52 ,  H05K1/03 ,  H01L23/373 ,  C04B111/00

CPC classification number: H05K1/09 ,  C04B41/009 ,  C04B41/52 ,  C04B41/90 ,  C04B2111/00405 ,  C04B2111/00844 ,  H01L23/15 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/3736 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/245 ,  H05K3/38 ,  H05K2201/0269 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2203/1126 ,  C04B35/00 ,  C04B35/10 ,  C04B35/185 ,  C04B35/48 ,  C04B35/581 ,  C04B35/584 ,  C04B41/4539 ,  C04B41/4572 ,  C04B41/5022 ,  C04B41/5127 ,  C04B41/5116 ,  C04B41/522 ,  C04B41/5155 ,  H01L2924/00

Abstract: A circuit board is provided with a metal wiring layer 12 on at least one principal surface of a ceramic sintered body 11, wherein the above-described metal wiring layer includes a first region 12a which is in contact with the principal surface and which contains a glass component and a second region 12b which is located on the first region 12a and which does not contain a glass component, the thickness of the first region 12a is 35% or more and 70% or less of the thickness of the metal wiring layer 12, and the average grain size in the first region 12a is smaller than the average grain size in the second region 12b.

Abstract translation: 电路板在陶瓷烧结体11的至少一个主面上设置有金属布线层12，其中上述金属布线层包括与主表面接触且包含玻璃的第一区域12a 第一区域12a和第二区域12b位于第一区域12a上并且不包含玻璃成分，第一区域12a的厚度为金属布线层12的厚度的35％以上且70％以下， 并且第一区域12a中的平均晶粒尺寸小于第二区域12b中的平均晶粒尺寸。

公开(公告)号：US20150223325A1

公开(公告)日：2015-08-06

申请号：US14612638

申请日：2015-02-03

Applicant: Seiko Epson Corporation

Inventor： Tetsuro MIYAO ,  Hideki ISHIGAMI ,  Yukihiko SHIOHARA ,  Tetsuya OTSUKI ,  Hidefumi NAKAMURA

IPC: H05K1/02 ,  H05K3/40 ,  H05K1/11 ,  H05K1/18 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1319 ,  H01L2224/16235 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81471 ,  H01L2224/8148 ,  H01L2224/81484 ,  H01L2224/8185 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/16251 ,  H01L2924/164 ,  H05K1/0306 ,  H05K1/09 ,  H05K1/092 ,  H05K1/115 ,  H05K1/184 ,  H05K3/1291 ,  H05K3/4061 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/10083 ,  H05K2201/1056 ,  H05K2203/1126 ,  H05K2203/1131 ,  H05K2203/1194

Abstract: A base substrate includes a ceramic sintered substrate having through holes, first and second metal wirings which are integrally disposed so as to be connected to the surface of the ceramic sintered substrate and the inside of the through holes, and first and second active metal layers which are disposed between the ceramic sintered substrate and the first and second metal wirings.

Abstract translation: 基底基板包括具有通孔的陶瓷烧结基板，一体地设置成连接到陶瓷烧结基板的表面和通孔内部的第一和第二金属布线以及第一和第二有源金属层， 设置在陶瓷烧结基板和第一和第二金属布线之间。

公开(公告)号：US20140239504A1

公开(公告)日：2014-08-28

申请号：US13779917

申请日：2013-02-28

Applicant: Hwei-Ling Yau ,  David Paul Trauernicht ,  John Andrew Lebens ,  Yongcai Wang ,  Ronald Steven Cok

Inventor： Hwei-Ling Yau ,  David Paul Trauernicht ,  John Andrew Lebens ,  Yongcai Wang ,  Ronald Steven Cok

IPC: H01L33/42

CPC classification number: G01N27/126 ,  G01N27/07 ,  G02F1/13439 ,  G06F3/044 ,  G06F2203/04103 ,  H05K3/0014 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0112 ,  H05K2201/0257 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/2054 ,  H05K2203/0108 ,  H05K2203/1131 ,  H05K2203/1476

Abstract: A multi-layer micro-wire structure includes a substrate having a surface. A plurality of micro-channels is formed in the substrate. A first material composition is located in a first layer only in each micro-channel and not on the substrate surface. A second material composition different from the first material composition is located in a second layer different from the first layer only in each micro-channel and not on the substrate surface. The first material composition in the first layer and the second material composition in the second layer form an electrically conductive multi-layer micro-wire in each micro-channel.

Abstract translation: 多层微线结构包括具有表面的基板。 在基板上形成多个微通道。 第一材料组合物仅位于每个微通道中的第一层中，而不位于基底表面上。 不同于第一材料组合物的第二材料组合物仅位于每个微通道而不是在基板表面上的不同于第一层的第二层中。 第一层中的第一材料组合物和第二层中的第二材料组合物在每个微通道中形成导电多层微线。

公开(公告)号：US08747579B2

公开(公告)日：2014-06-10

申请号：US12037958

申请日：2008-02-27

Applicant: Yoshikazu Oshika ,  Munenori Hashimoto ,  Masayuki Nakano

Inventor： Yoshikazu Oshika ,  Munenori Hashimoto ,  Masayuki Nakano

IPC: C22F1/14

CPC classification number: H05K3/3463 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1301 ,  H01L2924/157 ,  H01L2924/15787 ,  H05K2201/0269 ,  H05K2203/1105 ,  H05K2203/1157 ,  Y10T29/49149 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A solder layer and an electronic device bonding substrate having high bonding strength of a device and low bonding failure even by a simplified bonding method of a device to a substrate and a method for manufacturing the same are provided.A device bonding substrate 1 including a substrate 2 and a lead free solder layer 5 formed on said substrate has a solder layer 5 consisting of a plurality of layers having mutually different phases, and oxygen concentration on the upper surface of the solder layer is lower than 30 atomic % of the concentration of the metal component which is the most oxidizable among the metal components making up the upper layer of the solder layer 5. Carbon concentration on the upper surface of the solder layer 5 may be lower than 10 atomic % of the concentration of the metal component which is the most oxidizable among the metal components making up the upper layer of the solder layer.

Abstract translation: 提供了一种焊接层和具有高的器件结合强度和低接合故障的电子器件接合衬底，即使通过简化的器件对衬底的接合方法及其制造方法也是如此。 包括形成在所述基板上的基板2和无铅焊料层5的器件接合基板1具有由具有相互不同相的多个层构成的焊料层5，焊料层的上表面的氧浓度低于 在构成焊料层5的上层的金属成分中最可氧化的金属成分的浓度的30原子％。焊料层5的上表面的碳浓度可以低于焊料层5的10原子％ 在构成焊料层的上层的金属成分中最可氧化的金属成分的浓度。

公开(公告)号：US20120301824A1

公开(公告)日：2012-11-29

申请号：US13569375

申请日：2012-08-08

Applicant: Takahiro YOSHIDA ,  Shouji Minegishi ,  Masao Arima

Inventor： Takahiro YOSHIDA ,  Shouji Minegishi ,  Masao Arima

IPC: G03F7/004

CPC classification number: G03F7/095 ,  G03F7/004 ,  G03F7/0047 ,  H05K3/285 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068

Abstract: In a layered structure having at least a substrate and a photosensitive resin layer or cured film layer formed on the substrate and containing an inorganic filler, the content of the inorganic filler in the photosensitive resin layer or cured film layer is low on the side contacting the substrate and high on the surface side away from the substrate, so that a linear thermal expansion coefficient of the photosensitive resin layer or cured film layer as a whole is maintained as low as possible. Preferably, the inorganic filler content in the layer gradually increases continuously obliquely or stepwise from the side contacting the substrate to the surface side away from the substrate. A photosensitive dry film containing the above-mentioned photosensitive resin layer is suitable for use as a solder resist or an interlayer resin insulation layer of a printed wiring board.

Abstract translation: 在至少具有基板和形成在基板上并含有无机填料的感光性树脂层或固化膜层的分层结构中，感光性树脂层或固化膜层中的无机填料的含量在与 基板，并且远离基板的表面侧高，使得整个感光性树脂层或固化膜层的线性热膨胀系数保持尽可能低。 优选地，层中的无机填料含量从接触基板的表面侧离开基板的角度或逐步地逐渐增加。 含有上述感光性树脂层的感光性干膜适合用作印刷电路板的阻焊剂或层间树脂绝缘层。