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    Continuously Referencing Signals Over Multiple Layers in Laminate Packages
    91.
    发明申请
    Continuously Referencing Signals Over Multiple Layers in Laminate Packages 有权
    连续引用层叠软件包中多层信号

    公开(公告)号：US20090256253A1

    公开(公告)日：2009-10-15

    申请号：US12490872

    申请日：2009-06-24

    Applicant: Francesco Preda ,  Lloyd A. Walls

    Inventor： Francesco Preda ,  Lloyd A. Walls

    IPC: H01L23/12 ,  H01L21/50 ,  G06F17/50

    CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

    Abstract translation: 用于在层压封装中连续地参考多层信号的机构提供了用于从一层到另一层的信号的连续路径，同时使用用于封装的所有区域的理想电压基准并且仍避免电压基准中的不连续性。 参考平面调整引擎分析封装设计，并为封装的所有区域（包括特定芯片裸片下的区域）和不在芯片裸片下的区域识别理想的顶层平面。 参考平面调整引擎然后修改封装设计以重新定位层之间的接地层，源电压平面，信号面和通孔，以保持连续的电压基准，而不管顶层如何。 参考平面调整引擎将所得到的混合电压平面封装设计提供给设计分析引擎。 包装制造系统制造包装。

    LEADFRAME-BASED MODULE DC BUS DESIGN TO REDUCE MODULE INDUCTANCE
    93.
    发明申请
    LEADFRAME-BASED MODULE DC BUS DESIGN TO REDUCE MODULE INDUCTANCE 失效
    基于LEADFRAME的模块直流总线设计，以减少模块电感

    公开(公告)号：US20070193763A1

    公开(公告)日：2007-08-23

    申请号：US11673279

    申请日：2007-02-09

    Applicant: Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

    Inventor： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

    IPC: H05K9/00

    CPC classification number: H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H02M7/003 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K7/1432 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49009 ,  Y10T29/49117 ,  Y10T29/49126 ,  H01L2924/00

    Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

    Abstract translation: 用于电源模块的直流母线具有与负直流导体总线板平行的正直流导体母线板。 一个或多个正极引线连接到正极母线，并且可连接到电源的正极端子。 一个或多个负极引线连接到负母线并且可连接到电源的负极端子。 DC总线具有一个或多个正极连接，可从正极母线固定到电源模块的高侧。 DC总线还具有一个或多个从负母线固定到电源模块的低端的负极连接。 正母线和负母线允许电流逆流，从而消除磁场及其相关的电感，正负母线可连接到电源模块的中心部分。

    Printed circuit board having outer power planes
    95.
    发明授权
    Printed circuit board having outer power planes 有权
    具有外部电源平面的印刷电路板

    公开(公告)号：US07016198B2

    公开(公告)日：2006-03-21

    申请号：US10408951

    申请日：2003-04-08

    Applicant: John Thomas Fessler ,  Keith Bryan Hardin ,  Eric Wayne Westerfield

    Inventor： John Thomas Fessler ,  Keith Bryan Hardin ,  Eric Wayne Westerfield

    IPC: H05K7/06 ,  H05K9/00

    CPC classification number: H05K1/0218 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/09772 ,  H05K2201/10689

    Abstract: A multi-layer printed circuit board (PCB) routes signal traces on internal signal layer(s) and includes power planes on the two outermost layers. The outer layers are maintained at the same non-ground voltage level, and are electrically connected by a series of vias that circumscribe signal traces on the internal layer(s). With a preferred maximum spacing of one-tenth the wavelength of electromagnetic energy generated by the signal traces, the vias, together with the outer power planes, contain electromagnetic energy within the PCB. One or more of the outer planes may include a second power plane area maintained at a different voltage. The two power plane areas are connected by decoupling capacitors, located proximate underlying signal traces that traverse the two power plane areas.

    Abstract translation: 多层印刷电路板（PCB）在内部信号层上传送信号迹线，并且包括两个最外层的电源层。 外层保持在相同的非接地电压电平，并且通过一系列通孔来电连接，这些通孔围绕内层上的信号迹线。 通过由信号迹线产生的电磁能量波长的十分之一的优选最大间距，通孔与外部电源平面在PCB内包含电磁能。 一个或多个外平面可以包括维持在不同电压的第二电源平面区域。 两个电力平面区域通过去耦电容器连接，位于邻近穿过两个电源平面区域的底层信号迹线。

    Electronic control apparatus
    96.
    发明申请
    Electronic control apparatus 有权
    电子控制装置

    公开(公告)号：US20050047032A1

    公开(公告)日：2005-03-03

    申请号：US10928172

    申请日：2004-08-30

    Applicant: Mitsuhiro Kanayama ,  Toru Itabashi

    Inventor： Mitsuhiro Kanayama ,  Toru Itabashi

    IPC: H02M3/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H02H7/00

    CPC classification number: H02M3/00 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10166

    Abstract: An electronic control apparatus includes an exclusive power source wiring for a charge pump circuit which is discriminated from a common power source wiring. The exclusive power source wiring is connected to the common power source wiring via a via-hole va having the impedance larger than that of the wiring pattern. Similarly, the electronic control apparatus includes an exclusive ground wiring for the charge pump circuit which is discriminated from a common ground wiring. The exclusive ground wiring is connected to the common ground via an additional via-hole vb. Furthermore, a noise-suppressing capacitor C is connected between a power source wiring and a ground wiring. The power source wiring interposes between the via-hole va and the exclusive power source wiring, and the ground wiring interposes between the via-hole vb and the exclusive ground wiring.

    Abstract translation: 电子控制装置包括用于与公共电源布线区分开的用于电荷泵电路的专用电源布线。 专用电源布线经由具有比布线图案的阻抗大的阻抗的通孔va连接到公共电源布线。 类似地，电子控制装置包括用于与公共接地布线区分开的用于电荷泵电路的专用接地布线。 专用接地线通过附加的通孔vb连接到公共地。 此外，噪声抑制电容器C连接在电源布线和接地布线之间。 通孔va和专用电源布线之间的电源布线插入，并且接地布线插入通孔vb和专用接地布线之间。

    [LAYOUT STRUCTURE AND METHOD FOR SUPPORTING TWO DIFFERENT PACKAGE TECHNIQUES OF CPU ]
    97.
    发明申请
    [LAYOUT STRUCTURE AND METHOD FOR SUPPORTING TWO DIFFERENT PACKAGE TECHNIQUES OF CPU ] 有权
    [支持CPU的两种不同包装技术的布局结构和方法]

    公开(公告)号：US20040251534A1

    公开(公告)日：2004-12-16

    申请号：US10710731

    申请日：2004-07-30

    Inventor： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/119 ,  H01L031/113 ,  H01L023/52

    CPC classification number: H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

    Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

    Abstract translation: 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以被 相同的控制芯片。

    Multi-layered printed wiring board
    98.
    发明授权
    Multi-layered printed wiring board 失效
    多层印刷线路板

    公开(公告)号：US06800814B2

    公开(公告)日：2004-10-05

    申请号：US10046163

    申请日：2002-01-16

    Applicant: Tohru Ohsaka

    Inventor： Tohru Ohsaka

    IPC: H05K103

    CPC classification number: H05K1/0216 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09354

    Abstract: A multi-layered printed wiring board capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

    Abstract translation: 一种多层印刷电路板，即使在布线层数量减少并且减少辐射噪声的情况下也能够确保所需的布线密度。 多层印刷电路板具有至少三个布线层，每个布线层至少具有至少一个电源线或接地线，并且另一种线，所述布线层各自具有外边缘。 在至少一个布线层的外边缘处形成接地线。 在地线内形成基本电源线。 至少一条电源线从基本电源线延伸。 多个电子部件安装在至少一个布线层上。 所述至少一个电源线经由所述布线层中的至少一个布线到所述电子部件的安装位置。

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